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I am trying to bitshift a std_logic_vector, but no matter what I try, I always get an error.

I I have tried to use srl and also shift_right, which I read is safer to use. Both of them are not accepted by the compiler or at least I am making a syntax error, that I can't find. I also tried to cast the result to std_logic_vector.

library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity EXAMPLE is
    port(
        VOL_LEVEL           : in integer range 1 to 10; -- from AUDIO_VOL
        LED_OUT             : out std_logic_vector(9 downto 0)
    );
end entity EXAMPLE;

architecture BEHAVIOUR of EXAMPLE is

type STATES is (S_SET_VOL);

signal STATE, NEXT_STATE : STATES;

EXAMPLE: process(VOL_LEVEL)
begin
    case STATE is
        when S_SET_VOL =>

        LED_OUT <= ("1111111111") srl (10-VOL_LEVEL) after 2 ns; 
         -- Type error resolving infix expression "srl" as type ieee.std_logic_1164.STD_LOGIC_VECTOR.

        LED_OUT <= shift_right(unsigned("1111111111"), 10-VOL_LEVEL) after 2 ns;
         -- No feasible entries for subprogram "SHIFT_RIGHT".

        LED_OUT <= std_logic_vector(shift_right(unsigned("1111111111"), 10-VOL_LEVEL)) after 2 ns;
         -- Type conversion (to UNSIGNED) cannot have string literal operand.

end process EXAMPLE;

end BEHAVIOUR;
neolith
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    I presume that this is a test bench? In an entity which you want to synthesize you cannot use time information. i.e. `after 2 ns` – dyslexicgruffalo May 01 '19 at 10:11
  • You need to tell us *which* error you get exactly. – mkrieger1 May 01 '19 at 10:17
  • I added comments – neolith May 01 '19 at 10:24
  • I have found in my use of VHDL that i prefer to write my own shifting functions, especially when you want to change the amount of shift which it looks like you will want to do. This can typically be achieved with a for loop and a section of pipelining. But again it depends as to whether you want it to be syntheizeable! – dyslexicgruffalo May 01 '19 at 10:38
  • The example should be complete now – neolith May 01 '19 at 11:02
  • The third version should work if you use `to_unsigned` instead of `unsigned`. – mkrieger1 May 01 '19 at 11:39
  • Possible duplicate of https://stackoverflow.com/questions/33650504/vhdl-extend-string-literal-to-std-logic-vector – mkrieger1 May 01 '19 at 11:40
  • The second one is obviously wrong because the function is called `shift_right`, not `right_shift`. – mkrieger1 May 01 '19 at 11:42
  • See also: https://stackoverflow.com/questions/9018087/shift-a-std-logic-vector-of-n-bit-to-right-or-left – mkrieger1 May 01 '19 at 11:43
  • I already tried solving it according to question 9018087 before, but something is not right with the syntax. There it also says to use "unsigned" and not "to_unsigned". – neolith May 01 '19 at 12:48

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