Generate statement inside an always block, Is it possible?

Question

I would like to know more information about Generate statements I know that you can replicate modules, and always blocks (like in the other post) but, Would it be possible to create a parametrized case like this?

always @ (negedge clk) 
 begin
if (state==1)
  begin
     case(CS_sel)
    begin
        generate
           genvar i;
           for (i=0; i<N_DACS; i=i+1)
         begin: for1
            i:begin
               num <= mod_in[(i+1)*BITS-1:i*BITS];
               div <= mod_out[(i+1)*BITS-1:i*BITS];
            end // i:
             end    // for1
        endgenerate
        default: begin
           num <= mod_in[BITS-1:0];
           div <= mod_out[BITS-1:0];
        end // default
    end  // case (CS_sel)
     endcase // case (CS_sel)
  end // if (state==1)
  end // always

First of all, I would like to know if this is possible and how could I do it,

After this, if you know another option to create a synchronous multiplexer in verilog, it would be great!

Thank you!

Possible duplicate of [Verilog generate/genvar in an always block](https://stackoverflow.com/questions/12504837/verilog-generate-genvar-in-an-always-block) — Qiu, May 10 '19 at 12:20
Thank you, I have seen that post before but it didn't solve my doubts — Iván P., May 10 '19 at 12:30
Tbh I dont really get the "intended use scenario". Could you elaborate on "create a synchronous multiplexer in verilog"? Just by looking at this code I am wondering why you dont use something like `if(CS_sel < N_DACS) begin num <= mod_in[BITS*CS_sel +:BITS]; div <= mod_out[BITS*CS_sel +:BITS]; end else //default stuff` — Christian B., May 10 '19 at 13:53
Nope, Verilog does not allow to add generate block inside procedural blocks. You have to duplicate whole block and maintain two versions between which You would be able to switch during compile time using combination of Parameter and generate block. This is big limitation of Verilog itself and in the past I've seen some designers that created own pre-process language using simple pragma based syntax to overcome this problem. — PrzemekS, May 10 '19 at 14:52
can you consider System Verilog? It would be straight forward to re-write your example in that language. You can do it in verilog, but it will be a bit of a mess. — Serge, May 10 '19 at 21:35
@ChristianB. thank you! I have tried something similar but it appears an error due to write it like this `num <= mod_in[BITS*( **CS_sel** +1) :BITS* **CS_sel**]´ because i didn't know this " **+:** " @PrzemekS Thank you, your info was very useful because in the future maybe i will think something similar and now i know that is impossible to use a genarate block inside procedural blocks. @Serge Thank you, i will consider it in the future, now i have chosen the @Christian option :) — Iván P., May 13 '19 at 08:42
Yes, I think that both of you (@ChristianB. and @PrzemekS) should post it as answer because your answer it was very useful for me and the answer of @PrzemekS it will be more useful for the rest of users because is more related with the topic: "Generate statement inside an always block, Is it possible?" Thank you for everything — Iván P., May 13 '19 at 10:26

score 1 · Answer 1 · answered May 13 '19 at 10:56

The generate block cannot be used inside a always block but have to be placed outside. So one has actually the possiblity to build multiple different always block and chose between them via generate if constructs.

But just by looking at the given code I suggest the use of a different approach using proper slicing with fixed width and flexible offset:

if(CS_sel < N_DACS) begin
    num <= mod_in[BITS*CS_sel +:BITS];
    div <= mod_out[BITS*CS_sel +:BITS];
end else begin 
    //default stuff
    num <= mod_in[BITS-1:0];
    div <= mod_out[BITS-1:0];
end

This works because it is effectively similar to

wire [BITS-1:0] subset0;

assign subset0 = mod_in >> (BITS*CS_sel);
[...]
num <= subset0[BITS-1:0];

The direct use of something like mod_in[(i+1)*BITS-1:i*BITS] is not possible as this would theoretically allow for flexible width which (standard) verilog does not support by now to the best of my knowledge.

Generate statement inside an always block, Is it possible?

1 Answers1