difference between Virtual address and Modified virtual address in ARM architecture

Question

I am new in arm and arm instruction set. in the document of ARM-Cortex A8 i have seen some commands like cache flush accept input address as MVA ( modified virtual address). there is any difference between "Modified Virtual Address" and "Virtual Address" and if yes how can convert an 32-bit long virtual address to MVA.

Answer 1

Modified virtual addresses are a consequence of using the Fast Context Switch Extension. The Modified Virtual Address includes a 7-bit Process ID in the upper portion of a 32-bit address with the requirement that those bits of the virtual address were zero. This allows TLB tags and cache virtual tags to use a 32-bit address that is not extended (tagged) with the Process ID (address space ID).

For a little more information see the Boston University blog post "Tagged TLBs and Context Switching" or Gilles Chanteperdrix and Richard Cochran's paper "The ARM Fast Context Switch Extension for Linux" (PDF).

Answer 2

TL;DR - MVA is an older ARM technology term and most modern OSs will not use it. Even if it is used, it only applies to user space code and device drivers can ignore the term with 'VA == MVA'.

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The MVA is a consequence of tagging cache data with some ID. The intent is that user space code in an OS can remain in cache over a context switch. In ARMv5 the FSCE (fast context switch extension) was introduced. This was not very successful at being integrated into Linux but was used in products like the OKL4 hypervisor.

Many OSs are structured to start user space at low location, like 0x8000 making it easier to protect against NULL writes. So this FSCE allows multiple physical addresses to be mapped to the low address space. This means that cache need not be flushed on an OS context switch.

Armv6 introduces three other concepts to replace FSCE. First TTBR0 and TTBR1 to allow a split of OS/user page tables. Second Domains to partition libraries or logic memory groups. Third page entries can be non-global and assigned an ASID (address space id) via the CONTEXTIDR cp15 register and the GD bit of a page table entry. Here a flush/invalidate will only apply to the active ASID. So even though the cache is tagged there is no 'MVA'.

So MVA may apply only to user space code depending if the OS is using FSCE. For kernel and DMA/device memory you should always have VA=MVA on any ARM system. Generally you want it so your OS doesn't need to flush user memory as that is the whole point of these mechanisms.

Example

CP15 C7 cache maintenance.
c5 1 ICIMVAU Invalidate instruction cache line by address to PoU. Rt=Address

This CP15 register uses an 'MVA' to invalidate the L1. With FSCE, you can add the PID to the base address. With ASID, you must set that register prior to the call to do this invalidate. Again, most OSs would only do this for user space. Device and kernel memory do NOT use this mechanism in any normal circumstances.

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A major constraint of FSCE is that you have maximum of 128 processes and each process is limited to 2^25 or 32MB of size to take advantage of it. It also consumes a large amount of virtual address space. This is why it was never taken in to the Linux mainline. Even though many embedded Linux devices might benefit, it is not as generic as ASID, which support 256 processes does not have a size constraint and doesn't consume virtual address space.

• ARMv5 first architecture to have support of FSCE/PID/MVA.
• armv6 deprecates FSCE; always present, but shouldn't be used.
• armv7 makes FSCE optional; a cortex-A8 might have only stubs in silicon.
• armv8 doesn't have FSCE; never present, just stubs or RZ/WI registers.