DirectVHDL Warning C0007 : Architecture has unbound instance

Question

I am having trouble with a code I wrote. I keep getting an error when trying to simulate. Warning Warning C0007 : Architecture has unbound instance (ex. shifter2).

Here is my code. I am using DirectVHDL - PE

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;    
use ieee.std_logic_unsigned.all;

entity multi3 is
  port (   
    C : in std_logic_vector (7 downto 0);
    D : out std_logic_vector (10 downto 0));
end multi3;

architecture behavioral of multi3 is

component shifter
  port (
    Rin : in std_logic;
    A : in std_logic_vector(7 downto 0);
    B : out std_logic_vector(7 downto 0);
    Lout: out std_logic);
end component;

signal E, F : std_logic_vector (7 downto 0);
signal L1, L2 : std_logic;

begin

shifter1 : shifter port map('0',C,E,L1);

shifter2 : shifter port map('0',E,F,L2);

D<=('0' & L1 & L2 & F)+C;

end Behavioral;