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I am new to the assembly language MIPS. I am studying how to implement new instructions to the set in MIPS. I get that there is no need for a "subi" instruction, we can do it by "addi" with a negative number hovewer, if we implement this new instruction how would we do it?

(This I-type instruction subtracts, using a sign-extended immediate value. subi $t2, $t7, 4)

Its RTL would look like this I assume:

IM[PC]
RF[rd] <- RF[rs] – RF[rt]
PC <- PC + 4

Now is the tricky part, how do i implement this instruction to this simplified MIPS architecture (see image below)? (By introducing new muxes/control signals etc, any way necessary)

Is there an inverter nodule which inverts the immediate value, so i can put it after sign extention, add a mux to chose between + and - and be done with it? Or it needs something else?

Simplified MIPS Architecture

Peter Cordes
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Can Cavcav
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  • The ALU can already do subtraction. All you need to do is decode your new `subi` instruction and set the ALU control signals to subtraction. Also your RTL is obviously broken as it doesn't use the immediate :) – Jester Nov 24 '19 at 16:49
  • Ah thanks! Yes I see the mistake now ^^ – Can Cavcav Nov 24 '19 at 17:09
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    I'm voting to close this question as off-topic because it is not a computer programming question. It is a computer processor design question. – Raymond Chen Nov 24 '19 at 17:41
  • Where should I post questions similar to this? – Can Cavcav Nov 24 '19 at 17:44
  • From which university do you have this image? Just wondering because I had exactly the same. – AndiCover Nov 24 '19 at 18:34
  • bilkent university – Can Cavcav Nov 24 '19 at 22:10
  • Can't you just feed the register + immediate to the ALU and tell it to subtract (with trapping on signed overflow), the same way it does for a `sub` instruction? I mean, aren't `add` and `addi` implemented with the same ALU controls but different inputs? – Peter Cordes Nov 25 '19 at 00:12
  • And BTW, this might be on-topic on electronics.SE. – Peter Cordes Nov 25 '19 at 00:15
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    if you use some HDL language then it'll be on-topic here but you need to show the Verilog or VHDL code. The way to implement it is the same as how you implement add and sub with the same adder with a mux and a NOT gate. See [How does the CPU do subtraction?](https://stackoverflow.com/a/56279548/995714) – phuclv Nov 25 '19 at 06:39

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