Non delayed branch instruction MIPS

Question

I am currently reading the textbook Computer Organization and Architecture by David A Patterson and John L. Hennessy.

What does non delayed branch instruction mean in MIPS architecture?

Answer 1

A branch instruction with no branch-delay slot.

In the taken case, the instruction after the branch is not executed before the first instruction at the branch target. (Unlike traditional MIPS branches where it is taken, to hide branch latency without branch prediction or speculative execution. Forcing the compiler to statically schedule something hopefully-useful into that slot)

MIPS introduced these in 2014, in MIPS32r6 / MIPS64r6 according to Wikipedia:

a new family of branches with no delay slot:

• unconditional branches (BC) and branch-and-link (BALC) with a 26-bit offset,
• conditional branch on zero/non-zero with a 21-bit offset,
• full set of signed and unsigned conditional branches compare between two registers (e.g. BGTUC) or a register against zero (e.g. BGTZC),
• full set of branch-and-link which compare a register against zero (e.g. BGTZALC).

And an index jump instructions with no delay slot designed to support large absolute addresses.

Note the C suffix tacked on to previous branch mnemonics.

---

Also note that BGTUC reg, reg, target for example is a new thing. Original MIPS kept branch conditions simple so they could be evaluated in only half a cycle, so it only needed 1 branch delay slot to fully hide branch latency.

This microarchitectural reason is long gone with modern microarchitectures that can do branch prediction, so adding real HW branch instructions (instead of pseudo-instructions like classic bgtu reg, reg, target) saves an slt into a register.

Not having a branch delay slot is microarchitecturally unrelated to the new 2-register conditions other than eq and ne. They got added because MIPS32/64 r6 was reorganizing opcodes anyway, not because dropping a branch-delay slot made them possible.