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I am starting to learn SystemVerilog. I am stuck with a priority encoder and can't get this part :

priority if (encoder_in == {{14{1'bx}},1'b1,{1{1'b0}}})
dave_59
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Coolestjig
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    Does this answer your question? [What do curly braces mean in Verilog?](https://stackoverflow.com/questions/2102746/what-do-curly-braces-mean-in-verilog) – pr0f3ss Dec 18 '19 at 00:18

1 Answers1

2

this is actually a concatenation of 3 constants. 

{  {14{1'bx}}, 1'b1, {1{1'b0}}  }
1--^^^^^^^^^^ 
2--------------^^^^
3--------------------^^^^^^^^^

  1. is a replication operator and it generates a 14-bits of 'x'.

  2. is a one-bit 1

  3. is a replication operator with a single repetition. I have no idea why it is used this way.

The following would be an equivalent expression:

{{14{1'bx}}, 1'b1, 1'b0}

or this

{{14{1'bx}}, 2'b10}

or this:

 16'xxxxxxxxxxxxxx10

Next, priority is a system verilog modifier which could be applied to an if or a case operators. Read about unique end priority modifiers in system verilog.

Serge
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