Makefile to compile multiple C programs?

Question

This is an incredibly simple question, but I'm new to makefiles. I am trying to make a makefile that will compile two independent programs:

program1:
    gcc -o prog1 program1.c

program2:
    gcc -o prog2 program2.c

All the examples online go into way more details than I need and are confusing! All I really want it to do is to run the two gcc lines. What am I doing wrong?

The answers bellow are very clear, but you can also just run the command line: `make program1 program2` that will invoke both targets in the very example you gave yourself. If you just want `program1`, you can run just `make` (it will run the first target). If you just want `program2`, run `make program2`. You have more control. And of course, a target `all: program1 program2` will do just that (being it the first, running your 2 other targets). Done. — DrBeco, Jun 16 '16 at 05:31
12 years and still not a fulfilling answer? I'm also new to `make` and learned a lot from the answers below. — ranemirusG, May 28 '23 at 16:47

score 99 · Answer 1 · answered May 10 '11 at 13:03

99

Do it like so

all: program1 program2

program1: program1.c
    gcc -o program1 program1.c

program2: program2.c
    gcc -o program2 program2.c

You said you don't want advanced stuff, but you could also shorten it like this based on some default rules.

all: program1 program2

program1: program1.c
program2: program2.c

answered May 10 '11 at 13:03

cnicutar

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Note that if you want both programs to be built automatically, the `all` target must appear before the individual programs in the makefile, and be the first target in the makefile. – Randall Cook Jan 08 '14 at 02:15
3

You can put `all` or any other target wherever you want and make it the default for target-less (what you called "automatic") runs of `make` using `.DEFAULT_GOAL:=all`. – underscore_d Sep 19 '15 at 21:08

hmofrad · Answer 2 · 2018-01-08T16:20:47.740

40

Pattern rules let you compile multiple c files which require the same compilation commands using make as follows:

objects = program1 program2
all: $(objects)

$(objects): %: %.c
        $(CC) $(CFLAGS) -o $@ $<

edited Jan 08 '18 at 16:20

answered Apr 12 '17 at 02:56

hmofrad

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Instead of program1 and program2, what if you have thousands of ".c" files in various directories, sub-directories. How can we automate the same using above logic? – SH' Jan 22 '21 at 16:19
2

@SH' Use Make `shell` command to populate `objects` using the output of `find`. E.g., `objects := $(shell find . -type f -iname "*.c" -print | tr -d ".c" | sed 's/\///') ` – hmofrad Jan 22 '21 at 18:33
2

@hmofrad answer with 'tr' will remove all matching characters ['.', 'c'], not a substring. Fix: `find tests/ -type f -iname '*.cpp' | sed 's/.cpp//g'` – Ben Crowhurst Jul 01 '21 at 03:47
I'm using this for learning c++. To quickly compile and test little scripts. What other use cases may be that require this config? – ranemirusG May 28 '23 at 16:51

Robert · Answer 3 · 2012-12-04T04:27:07.020

############################################################################
# 'A Generic Makefile for Building Multiple main() Targets in $PWD'
# Author:  Robert A. Nader (2012)
# Email: naderra at some g
# Web: xiberix
############################################################################
#  The purpose of this makefile is to compile to executable all C source
#  files in CWD, where each .c file has a main() function, and each object
#  links with a common LDFLAG.
#
#  This makefile should suffice for simple projects that require building
#  similar executable targets.  For example, if your CWD build requires
#  exclusively this pattern:
#
#  cc -c $(CFLAGS) main_01.c
#  cc main_01.o $(LDFLAGS) -o main_01
#
#  cc -c $(CFLAGS) main_2..c
#  cc main_02.o $(LDFLAGS) -o main_02
#
#  etc, ... a common case when compiling the programs of some chapter,
#  then you may be interested in using this makefile.
#
#  What YOU do:
#
#  Set PRG_SUFFIX_FLAG below to either 0 or 1 to enable or disable
#  the generation of a .exe suffix on executables
#
#  Set CFLAGS and LDFLAGS according to your needs.
#
#  What this makefile does automagically:
#
#  Sets SRC to a list of *.c files in PWD using wildcard.
#  Sets PRGS BINS and OBJS using pattern substitution.
#  Compiles each individual .c to .o object file.
#  Links each individual .o to its corresponding executable.
#
###########################################################################
#
PRG_SUFFIX_FLAG := 0
#
LDFLAGS := 
CFLAGS_INC := 
CFLAGS := -g -Wall $(CFLAGS_INC)
#
## ==================- NOTHING TO CHANGE BELOW THIS LINE ===================
##
SRCS := $(wildcard *.c)
PRGS := $(patsubst %.c,%,$(SRCS))
PRG_SUFFIX=.exe
BINS := $(patsubst %,%$(PRG_SUFFIX),$(PRGS))
## OBJS are automagically compiled by make.
OBJS := $(patsubst %,%.o,$(PRGS))
##
all : $(BINS)
##
## For clarity sake we make use of:
.SECONDEXPANSION:
OBJ = $(patsubst %$(PRG_SUFFIX),%.o,$@)
ifeq ($(PRG_SUFFIX_FLAG),0)
        BIN = $(patsubst %$(PRG_SUFFIX),%,$@)
else
        BIN = $@
endif
## Compile the executables
%$(PRG_SUFFIX) : $(OBJS)
    $(CC) $(OBJ)  $(LDFLAGS) -o $(BIN)
##
## $(OBJS) should be automagically removed right after linking.
##
veryclean:
ifeq ($(PRG_SUFFIX_FLAG),0)
    $(RM) $(PRGS)
else
    $(RM) $(BINS)
endif
##
rebuild: veryclean all
##
## eof Generic_Multi_Main_PWD.makefile

Thanks for the above code. I use it to compile my .c files. But if i change any of my myHeader.h files, then i need to re-save an the .c file before using 'make' or else it shows "make: Nothing to be done for `all'." whereas actually changes have been made in the .h file. Can we modify the make file to compile after any changes in .h files without re-saving the .c file? and thanks for the above code!!! — jatin3893, Feb 03 '13 at 15:09
"$(OBJS) should be automagically removed right after linking." Doesn't that lead to unnecessary recompilation and, thus, mostly defeat the point of `make`? — underscore_d, Sep 19 '15 at 21:07
In Linux, macOS there is no need to `PRG_SUFFIX`. If you don't want suffix, set `PRG_SUFFIX=""`. Else if you set `PRG_SUFFIX=` or remove that line like `#PRG_SUFFIX=.exe`, you will get the `error: no such file or directory: 'all.o'` error. — Hamid Rouhani, Mar 06 '18 at 17:14

score 10 · Answer 4 · answered May 10 '11 at 13:03

10

all: program1 program2

program1:
    gcc -Wall -o prog1 program1.c

program2:
    gcc -Wall -o prog2 program2.c

answered May 10 '11 at 13:03

Erik

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score 3 · Answer 5 · answered May 10 '11 at 13:07

3

all: program1 program2

program1:
    gcc -Wall -ansi -pedantic -o prog1 program1.c

program2:
    gcc -Wall -ansi -pedantic -o prog2 program2.c

I rather the ansi and pedantic, a better control for your program. It wont let you compile while you still have warnings !!

answered May 10 '11 at 13:07

Master C

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That is not what `-pedantic` is for. `-pedantic` will remove any non-ansi features that even `-ansi` permits. – cnicutar May 10 '11 at 13:15
3

To add to cnicutar's comment, `-Werror` will change warnings to errors. – jtniehof May 10 '11 at 14:09

Misha Tavkhelidze · Answer 6 · 2017-03-10T03:45:40.300

1

SRC = a.cpp b.cpp
BIN = $(patsubst %.cpp,%,$(SRC))

all: $(BIN)

clean:
    rm -f $(BIN)

.PHONY: all clean

make all will do:

c++     a.cpp   -o a
c++     b.cpp   -o b

If you set CXX and CXXFLAGS variables make will use them.

edited Mar 10 '17 at 03:45

answered Oct 25 '16 at 10:55

Misha Tavkhelidze

792
9
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Did you mean `a.cpp -o a`? – Shane Abram Mendez Mar 09 '17 at 22:14

score 1 · Answer 7 · answered May 10 '11 at 13:32

A simple program's compilation workflow is simple, I can draw it as a small graph: source -> [compilation] -> object [linking] -> executable. There are files (source, object, executable) in this graph, and rules (make's terminology). That graph is definied in the Makefile.

When you launch make, it reads Makefile, and checks for changed files. If there's any, it triggers the rule, which depends on it. The rule may produce/update further files, which may trigger other rules and so on. If you create a good makefile, only the necessary rules (compiler/link commands) will run, which stands "to next" from the modified file in the dependency path.

Pick an example Makefile, read the manual for syntax (anyway, it's clear for first sight, w/o manual), and draw the graph. You have to understand compiler options in order to find out the names of the result files.

The make graph should be as complex just as you want. You can even do infinite loops (don't do)! You can tell make, which rule is your target, so only the left-standing files will be used as triggers.

Again: draw the graph!.

M3RS · Answer 8 · 2020-04-20T16:02:23.300

1

This will compile all *.c files upon make to executables without the .c extension as in gcc program.c -o program.

make will automatically add any flags you add to CFLAGS like CFLAGS = -g Wall.

If you don't need any flags CFLAGS can be left blank (as below) or omitted completely.

SOURCES = $(wildcard *.c)
EXECS = $(SOURCES:%.c=%)
CFLAGS = 

all: $(EXECS)

edited Apr 20 '20 at 16:02

answered Apr 18 '20 at 10:11

M3RS

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Makefile to compile multiple C programs?

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