load 3D matrix with Verilog

Question

I'm trying to load initial values into a register matrix,

in this case the matrix is small but is there any other way to load the values into the matrix?

(maybe using a CSV file? or memory entity?)

Thank you!

wire [7:0]matrix [3:0][6:0]; 

assign matrix[0][0] = 00;
assign matrix[0][1] = 01;
assign matrix[0][2] = 02;
assign matrix[0][3] = 03;
assign matrix[0][4] = 04;
assign matrix[0][5] = 05;
assign matrix[0][6] = 06;

assign matrix[1][0] = 07;
assign matrix[1][1] = 08;
assign matrix[1][2] = 09;
assign matrix[1][3] = 10;
assign matrix[1][4] = 11;
assign matrix[1][5] = 12;
assign matrix[1][6] = 13;

assign matrix[2][0] = 14;
assign matrix[2][1] = 15;
assign matrix[2][2] = 16;
assign matrix[2][3] = 17;
assign matrix[2][4] = 18;
assign matrix[2][5] = 19;
assign matrix[2][6] = 20;

assign matrix[3][0] = 21;
assign matrix[3][1] = 22;
assign matrix[3][2] = 23;
assign matrix[3][3] = 24;
assign matrix[3][4] = 25;
assign matrix[3][5] = 26;
assign matrix[3][6] = 27;

score 1 · Answer 1 · answered Jan 21 '20 at 16:13

Since this matrix is a ROM, most synthesis tools allow $readmemh to be used for initialization.

reg [7:0]matrix [3:0][6:0]; 
initial $readmemh("file", matrix); // See the LRM for how to format the file.

If you can use SystemVerilog, then you would have more options, like using a function to initialize the array of wires.

load 3D matrix with Verilog

1 Answers1