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I wrote a simple Real Time Clock code. However in simulation it shows X instead of output bits, also a glitch after value "000001" in Seconds output. Waveform Picture.

Could you please advise what is wrong with the code?

VHDL Code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL; -- Enables Adding    

entity rtc_timer is
generic( CLK_FREQ : integer := 10);
port
( 
    nRST        : in std_logic;
    clk         : in std_logic;
    Seconds     : inout std_logic_vector(5 downto 0);
    Minutes     : inout std_logic_vector(5 downto 0);
    Hours       : inout std_logic_vector(4 downto 0)
);
end rtc_timer;

architecture Behavioral of rtc_timer is
signal counter : integer;

begin
    process(nRST, clk) 
    begin
        if rising_edge(clk) then
            -- Negative Reset Signal
            if nRST = '0' then
                counter <= 0;
                Seconds <= (others => '0');
                Minutes <= (others => '0');
                Hours   <= (others => '0');
            elsif counter = CLK_FREQ - 1 then
                counter <= 0;

                if Seconds = 59 then
                    Seconds <= (others => '0');

                    if Minutes = 59 then
                        Minutes <= (others => '0');

                        if Hours = 23 then
                            Hours <= (others => '0');
                        else Hours <= Hours + 1;
                        end if;

                    else Minutes <= Minutes + 1;
                    end if;

                else Seconds <= Seconds + 1;
                end if;

            else counter <= counter + 1;
            end if;

        end if;         
    end process;

end Behavioral;
Rusk Box
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    Misuse of INOUT ports. In traditional VHDL, make them BUFFER.. Otherwise make them OUT and compile for VHDL-2008 or newer. –  Mar 16 '20 at 19:26
  • Thanks! This solves the issue. – Rusk Box Mar 16 '20 at 19:45
  • Another issue I have - first second (from 0 to 1sec) is counted not properly. It should start from rising edge of nRST and count each two CLK cycles (or ten with older code). Waveform https://imgur.com/a/nCnW08c – Rusk Box Mar 16 '20 at 21:38
  • No, it should count 2 rising clock edges after the end of Reset. And it does. I'll let you find that one yourself, but this may help. https://stackoverflow.com/questions/13954193/is-process-in-vhdl-reentrant/13956532#13956532 –  Mar 16 '20 at 22:23
  • I was teaching VHDL yesterday. I remember saying that there were 3 solutions to this problem: buffer ports, VHDL-2008 or rewrite your code. I recommended not using buffer ports, because all the ports you connected `hours`, `minutes` and `seconds` to, would also have to become buffer ports, too. (Before VHDL 2008). [See this example](https://www.edaplayground.com/x/Yjx). So, if you are not using VHDL-2008, I would rewrite my code, by using separate internal signals for the coutner code and then connect them to the outputs using 3 concurrent assignments – Matthew Taylor Mar 17 '20 at 08:34

0 Answers0