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I want to use a BRAM for a model and store the output in another block of that BRAM. But when simulating, I get the following error:

[VRFC 10-3236] concurrent assignment to a non-net 'roundreg' is not permitted ["C:/Users/.../keccak_new2/keccak.v":58]

code :

56    reg [23:0] roundreg [1599:0];
57
58    ROUNDFUNC  RF1(.clk(clk), .in(roundreg[0]), .out(roundreg[1]));
Jack
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1 Answers1

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Module output's can only be connected to net types in Verilog and roundreg[1] is not a net. If possible, you can declare roundreg as wire [23:0] roundreg [1599:0] instead, though that might affect how the rest of your code works. Note that if you can use SystemVerilog, you can avoid these complexities, and use the logic type instead.

You can also look at this question to see how to infer block RAM for FPGA designs: How to initialize contents of inferred Block RAM (BRAM) in Verilog

Unn
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  • Thank you for your response.I use a block RAM to reduce latency between registers. When more than two models are used, transfering data between them have a large network delay after synthesis. Is there any way to reduce this delay? – Jack Mar 18 '20 at 22:44