VHDL Process Declaration

Question

PROCESS(X,Y)
BEGIN
 OUT<=X;
 OUT<=OUT or Y;
END PROCESS;

I'm new to VHDL and I was testing out ways to assign logic values. Would this statement be a possible way to OR two values?

Answer 1

Note: OUT is a reserved keyword in VHDL. I assume you mean to reference a signal, so I've changed its name to OUTSIGNAL.

I have copied the process block from the Question with the signal name updated:

PROCESS(X,Y)
BEGIN
 OUTSIGNAL<=X;
 OUTSIGNAL<=OUTSIGNAL or Y;
END PROCESS;

As written, the process would not work as intended. VHDL signal assignments don't take effect until process execution reaches the end of the process block (or a 'wait' statement). Later signal assignments effectively override any prior signal assignments to the same signal, so the OUTSIGNAL<=X; statement is ignored in favour of the subsequent OUTSIGNAL<=OUTSIGNAL or Y; statement. The resulting behaviour of the process as written, depending on the initial value of OUTSIGNAL, is likely to be a set-only latch with Y as the set input.

In order to implement an OR gate, you could modify your process as follows:

PROCESS(X,Y)
BEGIN
 OUTSIGNAL<=X or Y;
END PROCESS;

... but this sequential process reduces to one statement, so you can just write it as a concurrent statement and eliminate the process entirely:

OUTSIGNAL<=X or Y;

---

If you'd like to retain the process, you could use a variable as follows:

PROCESS(X,Y)
 VARIABLE temp : STD_LOGIC;
BEGIN
 TEMP:=X;
 TEMP:=TEMP OR Y;
 OUTSIGNAL<=TEMP;
END PROCESS;

Variables in a VHDL process can be referenced and (re)assigned in successive process statements in the way that variables are referenced and (re)assigned in most imperative software languages.