Do For Loops sum between or after iterations? Verilog

Question

I will use this example code to ask some general questions about for loops.

The following code is intended to create a simple multiplier function between two 3-bit numbers, a and b:

1   function [5:0] mult;
2     input [2:0] a,b;
3     reg [5:0] r;
4     integer i;
5   begin
6     if(a[0] == 1)
7       r = b;
8     else
9       r = 0;
10    for(i=1; i<=2; i = i+1) begin
11       if(a[i]==1)
12         r = r + b <<i;
13    end
14    mult = r;  // set function name equal to product
15  end
16  endfunction

I believe this gives the desired result but I can only make sense of it if:

1. Lines 7 or 9 (depending on line 6 obviously) add to the end result of the 'for loop' (which begins on line 10)
2. The definition of r from lines 7 or 9 is not carried into line 12 in the 'for loop'
3. Each iteration (or 'step') of the 'for loop' does not carry its calculated value for r from a prior index value i into a subsequent index value i

If these three conclusions are correct then I have these questions:

• Do 'For Loops' sum their iterations after all possible steps have been made?
• Do 'For Loops' not carry information about an identifier within the 'for loop' derived from one step to the next despite the same identifier appearing in both steps (r in this case)? Referring to line 12 here.
• How should I have known conclusion #1 was true? What is the underlying rule(s)?

Finally, I understand 'for loops' don't necessarily add, they simply repeat if the condition is met. Only in this example is the 'for loop' adding.

Answer 1

The logic here is very simple. Consider a=3 -> 011 and b=5 -> 101. You can calculate it use following scheme:

   101 (b=5)
x  011 (a=3)
 -----
   101 (t1)
  101  (t2)
+000   (t3)
 -----
=01111 (15)

Line 7 and 9 are used to calculate the value denoted as t1 and for-loop is used to calculate t2 and t3. So:

• Line 6: a[0]=1. Thus, r=00101 in line 7.
• Line 11 and i=1: a[1]=1. Thus, r=00101 + 101<<1 = 00101 + 1010 = 01111.
• Line 11 and i=2: a[2]=0. Thus, r=01111.

You should read about blocking and non-blocking assigments in Verilog.

Answer 2

There is no difference between the for loop in your example and a for loop in any other programming language. It works absolutely the same. All operators inside the always block are executed sequentially, there is no other dependency mechanism between them other than the line numbers.

Lines 7 or 9 (depending on line 6 obviously) add to the end result of the 'for loop' (which begins on line 10)

This is a normal if operator, as in any other language. It is executed first and assigns an initial value to r, depending on the value of a[0].

The definition of r from lines 7 or 9 is not carried into line 12 in the 'for loop'

not sure what you mean here. The previous if operator sets the initial value of r, which is used in the first taken if statement in the loop as r = r + b <<i;. The right hand side of the expression contains r and first time around it contains the initial value.

Each iteration (or 'step') of the 'for loop' does not carry its calculated value for r from a prior index value i into a subsequent index value i

As in any programming language, the value of r will be updated every iteration where the if statement is taken. This updated value will be used at the next iteration of the loop in the same expression r = r + b <<i;.

If these three conclusions are correct then I have these questions:

your conclusions are incorrect. So you have to re-think your further questions.