Reg data type in verilog

Question

I have a huge confusion in understanding the Reg Data type in verilog. I know that we use reg variable when we need to store a value(s) in this variable. But for example lets consider that we have 4x1 MUX , I see some codes creates the input as

input a 
input b 
input c
input d

And for the output as

output reg z

So my question why did we use reg data type for the output only ? Why we didn't used it in the input variables ?

Also can I use a shorthand notation for the declaration of these inputs as

input a[4]

Is this right ?

You do **not** have to have output as `reg` and you **can** have inputs as `reg` as well. — Serge, May 01 '20 at 01:02

score 0 · Answer 1 · answered Apr 30 '20 at 23:53

0

The default type is wire, so input a actually means input wire a. (And you can change the default with default_nettype.)

a[4] isn't really shorthand as the names will be a[0]/a[1]/a[2]/a[3] instead of a/b/c/d, but it will result in the same number of individual nets. Declaring an unpacked type like a[4] may require SystemVerilog, whereas you can use a packed type like [3:0] a for Verilog ports.

answered Apr 30 '20 at 23:53

Justin N

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Why can't we use input Reg a instead of wire ? – AAA May 01 '20 at 01:18
@AAA You can't set an input, so that wouldn't accomplish anything. You can probably do that though. – Justin N May 01 '20 at 01:21

score 0 · Answer 2 · answered May 01 '20 at 06:22

Module input ports are essentially continuous assignments from the signal you connect the port to in the module instance, to the port signal in the declaration. You should never make any kind of assignments to the input port from inside the module. Verilog requires any signal that has a continuous assignment to it be declared as a wire. The output port has the continuous assignment going the other direction, so signal connected in the instance has to be a wire, but inside, the port signal could be a wire or reg, depending on how you want to make an assignment to the port signal.

See this link for more details on wire versus reg.

Reg data type in verilog

2 Answers2