I have some difficulties understanding how sequential statements inside a vhdl process are synthesized.
The IEEE standard reference manual Std 1076-2008 states:
Sequential statements are used to define algorithms for the execution of a subprogram or process; they execute in the order in which they appear.
It's easy to understand how it works in simulation since simulation is done by a CPU, that is build for sequential execution. In this case the hardest thing is to simulate concurrent executions, and this is done with the trick of delta delays. But what about the synthesis? I don't understand how it is possible for two statements to be sequential in a fully logical architecture...
Any help ?
An example process:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity example is
Port (clk, rst, A : in STD_LOGIC; B : out STD_LOGIC);
end example;
architecture example_arch of example is
begin
process(clk, rst)
variable C : STD_LOGIC;
begin
if rst = '1' then
C := '0';
B <= '0';
elsif rising_edge(clk) then
if A = '1' then
E := '1';
else
E := '0';
end if;
-- then sequentially ?
if E = '1' then
B <= '1';
else
B <= '0';
end if;
end if;
end process;
end example_arch;
