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This is the question: Does clflush flush L1i? Intel ISA manual was not clear on that:

Invalidates from every level of the cache hierarchy in the cache coherence domain the cache line that contains the linear address specified with the memory operand. If that cache line contains modified data at any level of the cache hierarchy, that data is written back to memory

I would speculate by the wording

If that cache line contains modified data at any level of the cache hierarchy, that data is written back to memory.

So L1I left untouched. Is it the actual behavior of Intel CPUs?

Some Name
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    It appears L1i lines are also evicted. Running `perf stat -e mem_load_retired.l1_miss,frontend_retired.l1i_miss` with the program [here](https://pastebin.com/9MD9inDR) will show about 10M L1d and L1i miss when lin 12 is *not* commented. Otherwise only 2K misses are reported (for both caches). – Margaret Bloom Jun 13 '20 at 14:16
  • @MargaretBloom Thanks for the comment, but may I ask you why you used `mfence`. `clflush` (unlike `clflushopt`) has strict memory ordering guarantees. – Some Name Jun 13 '20 at 14:35
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    Oops, I didn't remember which was ordered and which was not. Thank you for remembering me :) – Margaret Bloom Jun 14 '20 at 10:03

1 Answers1

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clflush does what it says on the tin and flushes all caches: instruction, data, and unified. (And the decoded-uop cache). Margaret Bloom actually tested to confirm this.

Instruction caches can't ever be dirty so it makes sense that discussion of modified lines talks about data. Only write-back data caches can be dirty. Note that one of the intended purposes of clflush is to write-back dirty data to a non-volatile DIMM, so it's natural that the docs focus on data.

You're reading too much into the wording, perhaps based on a misconception that write-back is synonymous with flushing. A clean cache line (such as I-cache) can be flushed by simply dropping it, no write-back necessary. Note the difference between invd and wbinvd. The invd docs use "flush" as a synonym for "invalidate". (related: What use is the INVD instruction?)

From Intel's vol.2 ISA ref manual entry for clflush

The CLFLUSH instruction can be used at all privilege levels and is subject to all permission checking and faults associated with a byte load (and in addition, a CLFLUSH instruction is allowed to flush a linear address in an execute-only segment). Like a load, the CLFLUSH instruction sets the A bit but not the D bit in the page tables.

This doesn't explicitly say that it actually flushes I-cache in such regions, but it implies that flushing is relevant for such cases where data accesses aren't even possible.

Semi-related: Flush iCache in x86

Peter Cordes
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