Verilog unsigned non-restoring division. Syntax Error: "I give up" Icarus Verilog

Question

I wanted to know why my Iverilog Compiler throws the "I give up" error at the end of the module. The error is:

DivisionsSchaltwerk.v:64: syntax error I give up

There is the Verilog code for my Divisior using a changed version of the AQ shift unsigned non-restoring division algorithm. Column 64 is at the endmodule part.

module Division(
    input         clock,
    input         start,
    input  [31:0] a,
    input  [31:0] b,
    output [31:0] q,
    output [31:0] r
);
    reg[31:0] AQ;
    reg[31:0] B;
    reg[31:0] R;
    reg[5:0] count;
    reg running;

    assign q = AQ;
    assign r = R;
    
    always @(posedge clock) begin
        if (start) begin
            R <= 0;
            AQ <= a;
            B <= b;
            count <= 6'd32;
            running <= 1;
         end
        else if (count == 0) begin
            running <=0;
            if(R<0) begin
                R <= R + B;
            end
            else begin
                R <= R - B;
            end
        end
        if (running) begin
            if (R<0) begin
                R <= R<<1;
                R[0] <= AQ[32];
                AQ <= AQ<<1;
            end
               if(R<0) begin 
                    AQ[0] <= 0;
                    R <= R + B;
                    count <= count -6'd1;
                end
                else begin
                    AQ[0] <= 1;
                    R <= R - B;
                    count <= count - 6'd1;
                end
            end
            else begin
                R <= R<<1;
                R[0] <= AQ[32];
                AQ <= AQ<<1;
            end
                if(R<0) begin 
                    AQ[0] <= 0;
                    R <= R + B;
                    count <= count -6'd1;
                end
                else begin
                    AQ[0] <= 1;
                    R <= R - B;
                    count <= count - 6'd1;
                end                
endmodule

score 1 · Answer 1 · answered Jun 24 '20 at 10:12

1

Your code has 12 "begin" and 11 "end" words. Try correcting the indentation to spot the missing "end".

answered Jun 24 '20 at 10:12

Peter de Rivaz

33,126
4
46
75

toolic · Accepted Answer · 2020-06-24T12:17:06.623

Your code has 2 types of errors:

Compile error
Compile warnings

The compile error is the missing end in your always block. Other simulators, such as those on edaplayground, produce a slightly more useful (and common) error message such as:

endmodule
        |
xmvlog: *E,NOTSTT : expecting a statement [9(IEEE)].

Coupled with the inconsistent indentation of your code, this typically means mismatched begin/end pairs. Furthermore, you can use emacs to automatically re-indent your code:

emacs --batch DivisionsSchaltwerk.v -f verilog-batch-indent

You also get compile warnings such as:

            R[0] <= AQ[32];
                     |
xmelab: *W,BNDWRN : Bit-select or part-select index out of declared bounds.

You declared AQ as [31:0]. Did you really mean to use AQ[31]?

Here is your auto-indented always block with matching begin/end:

   always @(posedge clock) begin
      if (start) begin
         R <= 0;
         AQ <= a;
         B <= b;
         count <= 6'd32;
         running <= 1;
      end
      else if (count == 0) begin
         running <=0;
         if(R<0) begin
            R <= R + B;
         end
         else begin
            R <= R - B;
         end
      end
      if (running) begin
         if (R<0) begin
            R <= R<<1;
            R[0] <= AQ[32];
            AQ <= AQ<<1;
         end
         if(R<0) begin 
            AQ[0] <= 0;
            R <= R + B;
            count <= count -6'd1;
         end
         else begin
            AQ[0] <= 1;
            R <= R - B;
            count <= count - 6'd1;
         end
      end
      else begin
         R <= R<<1;
         R[0] <= AQ[32];
         AQ <= AQ<<1;
      end
      if(R<0) begin 
         AQ[0] <= 0;
         R <= R + B;
         count <= count -6'd1;
      end
      else begin
         AQ[0] <= 1;
         R <= R - B;
         count <= count - 6'd1;
      end                
   end

Verilog unsigned non-restoring division. Syntax Error: "I give up" Icarus Verilog

2 Answers2