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This is my code for SRAM simulation in pspice SRAM simulation

VDD 3 0 DC 5V

VWL 4 0 PWL (9us 0V 10us 5V 90us 5V 91us 0V)

VBL1 5 0 PWL (0 0V 1us 5V 100us 5V 101us 0V)

VBL2 6 0 PWL (0 0)

M1 1 2 3 3 PMOS

M2 1 2 0 0 NMOS

M3 2 1 3 3 PMOS

M4 2 1 0 0 NMOS

M5 5 4 1 1 NMOS

M6 6 4 2 2 NMOS

.MODEL NMOS NMOS (L=5um,W=30um,VTO=0.7)

.MODEL PMOS PMOS (L=5um,W=30um,VTO=-0.7)

.TRAN 0.2us 120us

.PLOT TRAN V(1)

.PROBE

However when I simulate I don't see the voltage to be stored in gate of the mosfet.Can anyone tell me what's wrong or what modification should I do in my code?

Psychofreak
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1 Answers1

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There are several problems in your circuit: M5 and M6 have a bulk diode that is connected (anode) to nodes 1 and 2 and (cathode) to node 5 and 6. If node 6 and node 5 are LOW (0V) the bulk diode wins no matter what you do at node 4. To get rid of the bulk diodes write:

M5 5 4 1 0 NMOS

M6 6 4 2 0 NMOS

(connects the bulk to node 0)

M5 and M6 must be stronger than M1 to M4. You must give them a higher width than M1..M4. Try W=100u for M5 and M6.

I'm missing the gate oxide thickness in your model. (tox=15n or similar), But may be your spice version has a nice default doing the job.

There is no .end statement telling spice this is the end of the code. So may be your spice interpreter is waiting for ever to find the end and start running.

Ricardo Erckert
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