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I built a custom board with a cyclone10GX and a phy marvell 88E1518 in RGMII mode. I had a similar hardware working fine using a cycloneIII and a marvell 88E1111 in RGMII mode too.

It failed to run the same design consisting of a full hardware UDP/IP stack at 1Gb.

I enabled a signaltap probe after the DDIO on the Reception path and the RX_CLK of the phy. This clock feeds an IOPLL driving everything inside the FPGA.
Surprisingly, the input clock RX_CLK goes down for some cycle and makes the PLL unlock.
systematic loss of lock at RX_Data_Valid random loss of lock

I continuously check some of the MDIO registers to understand what's happening. The register 10 page 0 tells it got IDLE Errors although I do nothing in particular. From what I know about 802.3, IDLE is the interpacket gap needed between 2 packets. In page 41 of the datasheet, it says :

In 1000BASE-T mode, the receive idle stream is analyzed so that the scrambler seed, the skew among the 4 pairs, the pair swap order, and the polarity of the pairs can be accounted for. Once calibrated, the 4D PAM 5 symbols are converted to 9-bit symbols that are then descrambled into 8-bit data values. If the descrambler loses lock for any reason, the link is brought down and calibration is restarted after the completion of Auto-Negotiation

I don't know where to check for errors. If anyone has a clue of what could happen, I would greatly appreciate the help.

John

NoRest NR
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  • in 1000BASE-T the IDLE character is sent when there is no data to be sent. The phy recovers the rx clk from the data stream. What do you have on the other side of the link? – PenguMC Oct 30 '20 at 12:44
  • There is a giga ethernet switch and my own computer on the other side. Nothing fancy. – NoRest NR Nov 01 '20 at 22:07
  • I retried with several different phase shift on the recovered rx clock from the IOPLL and there are still some errors. I do think this phy is broken. – NoRest NR Nov 01 '20 at 22:11
  • Another thing to try: run your receive path logic directly on the rx clock from the PHY, without PLL. The rx clock recovery will reset when either side restarts an autonegotiate, so make sure you're not continuously resetting the PHY through the MDIO – PenguMC Nov 02 '20 at 10:25
  • Hi I come back after a while just to mention that Cyclone10GX does not support RGMII. Receive path works properly but not TX. One more board to throw away ... – NoRest NR Dec 24 '20 at 10:33

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