VHDL instruction in process isn't executed

Question

I'm tasked with designing a cache and cache controller. I'm reading the 16 bytes for a block from memory and writing it to the cache. On the last byte of the block only, the data_array isn't updated and remains 0s. I've managed to isolate an unexpected behavior down to one instruction weirdly not executing.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity cache is
...
port(
    ...
    m_readdata : in std_logic_vector (7 downto 0);
    ...
);
end cache;

architecture arch of cache is

...
type Data_Array_Type is array (31 downto 0) of std_logic_vector(127 downto 0);
signal data_array : Data_Array_Type := (others=> (others=>'0'));
...

begin
  process(clock, reset)
    begin
      ...
      data_array (index) (127 downto 120) <= m_readdata;
      report "m_readdata: " & integer'image(to_integer(unsigned(m_readdata)));
      report "data_array (index) (127 downto 120): " & integer'image(to_integer(unsigned(data_array (index) (127 downto 120))));
      ...
    end process;
end arch;

This is the output.

# ** Note: m_readdata: 255
#    Time: 195500 ps  Iteration: 0  Instance: /cache_tb/dut
# ** Note: data_array (index) (127 downto 120): 0
#    Time: 195500 ps  Iteration: 0  Instance: /cache_tb/dut

The output shows the line assigning m_readdata to the data_array not executing somehow. Nowhere else is the data array being modified.

That's perfectly as expected. You may want to read up about signal assignment semantics. — , Mar 08 '21 at 20:50

score -2 · Answer 1 · answered Mar 08 '21 at 04:52

-2

This is super peculiar. Apparently it is because VHDL doesn't update values inside processes until the next run. It is more clearly explained here https://stackoverflow.com/a/13956532/7923070.

answered Mar 08 '21 at 04:52

L4mbo

43
4

2

It's because VHDL is a _hardware_ description language. You are designing hardware, not writing software. To be clear (to hopefully help in your understanding of what is happening), the line was executed (statements inside processes are executed sequentially, in order), but the signal assigned to by that line would not be updated until that process (and all others) suspend. A signal is a different construct to a variable (in any other software language and in VHDL). Signals behave differently to variables. – Matthew Taylor Mar 08 '21 at 07:14
1

VHDL describes an event driven virtual machine using signals and delta simulation cycles (where simulation time doesn't advance) to emulate parallelism. Signal updates occur in an earlier part of the simulation cycle than process resumption and subsequent suspension. An assigned signal waveform element without a non-zero `after time_expression` will cause a delta cycle. Here the second report statement executes in the same simulation cycle the assignment is scheduled. Processes communicate via signals, [use two processes](https://i.stack.imgur.com/gQClS.jpg). – Mar 08 '21 at 15:11

VHDL instruction in process isn't executed

1 Answers1