I am wondering what is the cost of multiplication operation in general purpose computers in terms of clock cycles. I mean what is the hardware or algorithm for multiplication. Is it Baugh-Wooley signed multiplication algorithm or Booth's algorithm or something else? Thanks for any information.
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Search for "alu multiplication" (along with any other relevant designator). The specifics - and especially the 'clock cycles' - will vary by specific implementation as opposed to nebulous 'general purpose computer'. – user2864740 Apr 30 '21 at 22:34
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Might be useful: https://stackoverflow.com/questions/26370287/how-modern-x86-processors-actually-compute-multiplications/62117473#62117473 , and https://stackoverflow.com/questions/37925143/x86-64-is-imul-faster-than-2x-shl-2x-add/37925245 – Renat Apr 30 '21 at 22:51
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For actually clock cycles, 3 cycles latency, fully pipelined at 1/clock throughput is common for integer multiply in modern x86; probably similar in other high-performance pipelines. But check their vendor's manuals. e.g. until Zen, AMD had slower performance for 64-bit multiply, vs. 32-bit integers. Renat's first link answers for all ISAs, not just the x86 in the title: Dadda trees. – Peter Cordes May 01 '21 at 00:16