What's the microarchitecture used in the MIPS I.S.A?

Question

I believed the microarchitecture used in a MIPS microprocessor, is the pipeline one, but I might be wrong?

Thanks in advance for your answers!

It doesn't really work like that, microarchitectures use an ISA, not the other way around. But MIPS was designed for pipelined implementations. — harold, May 13 '21 at 13:49
In case of MIPS, a lot of microarchitecture details are actually exposed into ISA (delay slots, etc.) — SK-logic, May 14 '21 at 08:23

score 0 · Accepted Answer · answered May 13 '21 at 14:32

MIPS is an ISA; you can implement it however you like. Some hobby projects implement it in a non-pipelined way, but the ISA was designed around a https://en.wikipedia.org/wiki/Classic_RISC_pipeline - in fact being easy to pipeline was the whole point of RISC, and of the Stanford MIPS project. (Commercial MIPS evolved out of that research project.)

The first commercial MIPS, R2000 was a 5-stage RISC which implemented the MIPS I ISA, was designed so that one branch delay slot was sufficient to hide branch latency.

But MIPS R10000 was a 4-wide superscalar out-of-order design with register renaming.

Other later MIPS implementations are embedded CPUs with shorter pipelines, and once again in-order execution. https://en.wikipedia.org/wiki/MIPS_architecture#Uses

See also Modern Microprocessors A 90-Minute Guide!

@Penguineer: If that fully answered your question, you can click the "accept" checkbox under the vote arrows. — Peter Cordes, May 13 '21 at 14:53

What's the microarchitecture used in the MIPS I.S.A?

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