Why does signal assignment not execute on the first iteration? VHDL

Question

I'm new to VHDL. I heard that signal assignment only updates at the end of a process and will only use the most recent assignment, so I wanted to test it out. How come the value for temp did not update at the end of the first process(i=0) even though I already have an initial value for a,b,c? It only started updating the value for temp on the second iteration(i=1).

Code I used to test:

architecture Behavioral of test is
    signal a    : integer := 1;
    signal b    : integer := 2;
    signal c    : integer := 3;
    signal i    : integer := 0;
    signal temp, temp2  : integer;
begin
    process is
    begin
        report "-----Start Here-----(" & integer'image(i) & ")";
        temp <= a;      report "1:" & integer'image(temp);
        temp <= b;      report "2:" & integer'image(temp);
        temp <= c;      report "3:" & integer'image(temp);

        temp2 <= a;     report "4:" & integer'image(temp2);
        temp2 <= temp;  report "5:" & integer'image(temp2);
        report "-----End Here----------------------------";
        
        i <= i + 1;
        wait for 10ns;
    end process;
end architecture;

OUTPUT:

-----Start Here-----(0)
1: -2147483648                  
2: -2147483648
3: -2147483648
4: -2147483648
5: -2147483648
-----End Here----------------------------
-----Start Here-----(1)
1: 3
2: 3
3: 3
4: -2147483648
5: -2147483648
-----End Here----------------------------
-----Start Here-----(2)
1: 3
2: 3
3: 3
4: 3
5: 3
-----End Here----------------------------

See the [answer to sequential execution in process statement in vhdl](https://stackoverflow.com/a/50163596/16145658) where the question's distinction from yours lies the use of a process sensitive to a clock event and the process only takes one clock to traverse. VHDL LRM extracts are used to describe what happens during simulation. — user16145658, Aug 24 '21 at 21:51

score 2 · Accepted Answer · answered Aug 24 '21 at 17:18

When a signal assignment occurs, it schedules the value to be updated when a process hits a wait statement (when there is no sensitivity list) or when the process completes (when there is a sensitivity list). In your process, at time 0, The process starts. temp has the initial value integer'low. You assign a, then b, then finally c (which wins, and temp will be scheduled to have c assigned). Remember, there is no wait statement hit by this point, so the signal assignments will not have occured yet. Hence why the report all report the initial value for temp.

If you move the report statments to be after the wait statement, you would see the updated values.

Why does signal assignment not execute on the first iteration? VHDL

1 Answers1