Verilog test bench for 4-bit adder with Carry Lookahead

Question

I'm still honestly a bit unfamiliar with Verilog especially with test benches, considering I've only created a childishly simple project once. I'm not sure how to make a test bench for a Verilog file I've made and so I can't test if it works. Here's my code:

`timescale 1ns/1ps

module adder_4bit_cla(sum, Cout, A, B, S);

    input [3:0] A, B;
    input S;
    output [3:0] sum;
    output Cout;
    
    wire P0, G0, P1, G1, P3, G3;
    wire C4, C3, C2, C1;
    
    assign
        P0 = A[0] ^ B[0],
        P1 = A[1] ^ B[1],
        P2 = A[2] ^ B[2],
        P3 = A[3] ^ B[3];
        
    assign
        G0 = A[0] & B[0],
        G1 = A[1] & B[1],
        G2 = A[2] & B[2],
        G3 = A[3] & B[3];
        
    assign
        C1 = G0 | (P0 & S),
        C2 = G1 | (P1 & G0) | (P1 & P0 & S),
        C3 = G2 | (P2 & G1) | (P2 & P1 & G0) | (P2 & P1 & P0 & S),
        C4 = G3 | (P3 & G2) | (P3 & P2 & G1) | (P3 & P2 & P1 & G0) | (P3 & P2 & P1 & P0 & S);
        
    assign
        sum[0] = P0 ^ S,
        sum[1] = P1 ^ C1,
        sum[2] = P2 ^ C2,
        sum[3] = P3 ^ C3;
        
    assign Cout = C4;
    
endmodule

Honestly, what I really need to do is a 4-bit adder-subtractor using carry lookahead, but I have no idea how to implement a carry lookahead to begin with so here I am. If anyone could help me that would be really great :<

Edit: I have calmed down and I can finally pinpoint the exact problem: the values of A and B for the test bench. While I could brute force it, how can I make use of loops to increment A and B so that it would be like this:

While also updating M?

In a testbench, you only need to consider about input and output signals. Based on given input signals, you can verify the behaviour of your output signal whether it behaves as expected. — Kavindu Vindika, Aug 28 '21 at 12:57
@KavinduVIndika sorry for the @ but if ever you are still interested in helping me solve, I've edited the post. — Marasmius, Aug 28 '21 at 13:21
Nice, that means you want to feed the input data in your testbench using a loop right ? — Kavindu Vindika, Aug 28 '21 at 13:23

Kavindu Vindika · Accepted Answer · 2021-08-28T13:32:44.367

0

Use the following to improve your testbench.

`timescale 1ns / 1ps

module adder_4bit_cla_tb();

// inputs - keep them having reg as the data type 
reg [3:0] A, B;
reg S;

// outputs - keep them having wire as the data type 
wire [3:0] sum;
wire Cout;


adder_4bit_cla adder_4bit_cla_inst
                  (
                 .sum(sum), .Cout(Cout), .A(A), .B(B), .S(S)
                  );

initial begin
       
    A = 4'd1; B = 4'd2; S = 1'd1;
    
    #10 A = 4'd2; B = 4'd5; S = 1'd0;
    
    #10 A = 4'd5; B = 4'd6; S = 1'd0;

    #50 $stop;
    
end
endmodule

Waveform results

Inputs can be fed using for loops as follows.


`timescale 1ns / 1ps

module adder_4bit_cla_tb();

// inputs - keep them having reg as the data type 
reg [3:0] A, B;
reg S;

// outputs - keep them having wire as the data type 
wire [3:0] sum;
wire Cout;

reg [3:0] i; 

adder_4bit_cla adder_4bit_cla_inst
                  (
                 .sum(sum), .Cout(Cout), .A(A), .B(B), .S(S)
                  );

initial begin
     
    for(i = 4'd0; i < 4'd15; i = i + 4'd1) begin  
    
    A = i; B = i; S = 1'b0;
    
    #10;
    
    end
    
    #200 $stop;
    
end
endmodule

Waveform Results

edited Aug 28 '21 at 13:32

answered Aug 28 '21 at 13:21

Kavindu Vindika

2,449
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Hello! I've pretty much gotten the `reg`s and `wire`s correct, but I'm not sure if I understand the code block starting from `initial begin` until `end`. Would I not need a loop to iterate over all possible values of `A` and `B`? – Marasmius Aug 28 '21 at 13:30
`Initial begin` to `end` represent complete process that you want to evaluate. Using `#{time}`, you can define how much time the relevant inputs needs to be stay intact without changing. In this case, timescale is given in **nano-seconds**. – Kavindu Vindika Aug 28 '21 at 13:36
By having `#10 A = 4'b2; B = 4'b3;`, you are giving 10 ns before feeding inputs in the process. When you have `#10` after feeding the inputs, then that means you're waiting for 10 ns after input feeding. – Kavindu Vindika Aug 28 '21 at 13:38
Hello, sorry one last thing. It took me a while because I was debugging something when I transferred a portion of your code to mine and changed variables. But I did encounter something: `S` doesn't change and it is constantly 0. Is this intended? – Marasmius Aug 28 '21 at 14:30
Yes, if you check this line `A = i; B = i; S = 1'b0;`, I'm feeding S with 0 for the complete process. You can feed it any value inside the for-loop and you can patternize it in the similar way I've done it with A and B as you can see in the above line. – Kavindu Vindika Aug 28 '21 at 14:33

Verilog test bench for 4-bit adder with Carry Lookahead

1 Answers1