library ieee;
use ieee.std_logic_1164.all;
entity F_A is
port(
a,b,c_in : in std_logic;
sum,c_out : out std_logic);
end F_A;
architecture behave of F_A is
begin
sum <= a xor b xor c_in;
c_out <= (a and b)or(a and c_in)or(b and c_in);
end behave;
library ieee;
use ieee.std_logic_1164.all;
entity Adder_4bit is
port( a,b: in std_logic_vector(3 downto 0);
Cin: in std_logic;
sum: out std_logic_vector(3 downto 0);
Cout: out std_logic);
end Adder_4bit;
architecture logic of Adder_4bit is
signal c : std_logic_vector(2 downto 0);
component F_A
port( a,b,c_in : in std_logic;
sum,c_out: out std_logic);
end component;
begin
FA0 : F_A
port map(a(0),b(0),Cin,sum(0),c(0));
FA1 : F_A
port map(a(1),b(1),c(0),sum(1),c(1));
FA2 : F_A
port map(a(2),b(2),c(1),sum(2),c(2));
FA3 : F_A
port map(a(3),b(3),c(2),sum(3), Cout);
end logic;
Library IEEE;
USE IEEE.Std_logic_1164.all;
entity Dff is
port(
Q : out std_logic;
Clk :in std_logic;
signal sync_reset: in std_logic;
D :in std_logic
);
end Dff;
architecture Behavioral of Dff is
begin
process(Clk)
begin
if(rising_edge(Clk)) then
if(sync_reset='1') then
Q <= '0';
else
Q <= D;
end if;
end if;
end process;
end Behavioral;
library ieee;
use ieee.std_logic_1164.all;
entity proj1 is
port( A, B, Ac, Bc: in STD_logic_vector(3 downto 0);
C: out STD_LOGIC_vector(3 downto 0):= "0000";
signal sync_reset: in std_logic;
s1,s2,ci: in STD_logic;
co : out STD_logic := '0');
end proj1;
architecture behavioral of proj1 is
Component Adder_4bit is
port( a,b: in std_logic_vector(3 downto 0);
Cin: in std_logic;
sum: out std_logic_vector(3 downto 0);
Cout: out std_logic);
end component;
Component Dff is
port(
Q : out std_logic;
Clk :in std_logic;
signal sync_reset: in std_logic;
D :in std_logic
);
end component;
begin
Dff0 : Dff
port map(A(0),clk, sync_reset, A(0));
Dff1 : Dff
port map(A(1),clk, sync_reset, A(1));
Dff2 : Dff
port map(A(2),clk, sync_reset, A(2));
Dff3 : Dff
port map(A(3),clk, sync_reset, A(3));
Dff4 : Dff
port map(B(0),clk, sync_reset, B(0));
Dff5 : Dff
port map(B(1),clk, sync_reset, B(1));
Dff6 : Dff
port map(B(2),clk, sync_reset, B(2));
Dff7 : Dff
port map(B(3),clk, sync_reset, B(3));
Dff8 : Dff
port map(s1,clk, sync_reset, s1);
Dff9 : Dff
port map(s2,clk, sync_reset, s2);
Dff10 : Dff
port map(ci,clk, sync_reset, ci);
process (ALU)
BEGIN
IF s2 = '0' and s1 = '0' and ci = '0' then
C(0)<=A(0);
C(1)<=A(1);
C(2)<=A(2);
C(3)<=A(3);
elsif s2 = '0' and s1 = '0' and ci = '1' then
adder0 : Adder_4bit
port map(A, "0001",Cin, C, Co);
elsif s2 = '0' and s1 = '1' and ci = '0' then
adder1 : Adder_4bit
port map(A, B,Cin, C, Co);
elsif s2 = '0' and s1 = '1' and ci = '1' then
adder2 : Adder_4bit
port map(A, B,Cin, Ac, Co);
adder3 : Adder_4bit
port map(Ac, "0001",Cin, C, Co);
elsif s2 = '1' and s1 = '0' and ci = '0' then
adder4 : Adder_4bit
port map(B, "1111",Cin, Bc, Co);
adder5 : Adder_4bit
port map(Bc Xor "1111" , "0001",Cin, Bc, Co);
adder6 : Adder_4bit
port map(A ,Bc ,Cin , C, Co);
elsif s2 = '1' and s1 = '0' and ci = '1' then
adder7 : Adder_4bit
port map(B Xor "1111" , "0001",Cin, Bc, Co);
adder8 : Adder_4bit
port map(A, Bc,Cin, Bc, Co);
elsif s2 = '1' and s1 = '1' then
C (0) <= A(0) Xor B(0);
C (1) <= A(1) Xor B(1);
C (2) <= A(2) Xor B(2);
C (3) <= A(3) Xor B(3);
end if;
end process;
end behavioral;
The errors are as follows:
Error (10500): VHDL syntax error at proj1.vhd(135) near text "port"; expecting "(", or "'", or "."
Error (10500): VHDL syntax error at proj1.vhd(135) near text ";"; expecting ":=", or "<="
Error (10500): VHDL syntax error at proj1.vhd(140) near text "port"; expecting "(", or "'", or "."
Error (10500): VHDL syntax error at proj1.vhd(140) near text ";"; expecting ":=", or "<="
Error (10500): VHDL syntax error at proj1.vhd(145) near text "port"; expecting "(", or "'", or "."
Error (10500): VHDL syntax error at proj1.vhd(145) near text ";"; expecting ":=", or "<="
Error (10500): VHDL syntax error at proj1.vhd(148) near text "port"; expecting "(", or "'", or "."
Error (10500): VHDL syntax error at proj1.vhd(148) near text ";"; expecting ":=", or "<="
Error (10500): VHDL syntax error at proj1.vhd(153) near text "port"; expecting "(", or "'", or "."
Error (10500): VHDL syntax error at proj1.vhd(153) near text ";"; expecting ":=", or "<="
Error (10500): VHDL syntax error at proj1.vhd(156) near text "port"; expecting "(", or "'", or "."
Error (10500): VHDL syntax error at proj1.vhd(156) near text ";"; expecting ":=", or "<="
Error (10500): VHDL syntax error at proj1.vhd(159) near text "port"; expecting "(", or "'", or "."
Error (10500): VHDL syntax error at proj1.vhd(159) near text ";"; expecting ":=", or "<="
Error (10500): VHDL syntax error at proj1.vhd(164) near text "port"; expecting "(", or "'", or "."
Error (10500): VHDL syntax error at proj1.vhd(164) near text ";"; expecting ":=", or "<="
Error (10500): VHDL syntax error at proj1.vhd(167) near text "port"; expecting "(", or "'", or "."
Error (10500): VHDL syntax error at proj1.vhd(167) near text ";"; expecting ":=", or "<="
And if it it is relevant and you have any assistance for my general project the goal is
S2 S1 Ci
0 0 0 => C=A
0 0 1 => C=A+1
0 1 0 => C=A+B
0 1 1 => C=A+B+1
1 0 0 => C=A-B-1
1 0 1 => C=A-B
1 1 N/A => C=A XOR B
The idea is that It uses D-flip flops to check if the inputs/output are valid. I also was hoping to get double checked that using the component with declared output variables in the process just directly sets them to the output value from the component. Because of some of the snippets I used from the internet it's still Vague to me. Very new to VHDL literally started using it less then 1 month ago. any advice appreciated!
