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module data_mem(
    input clk,
    input [31:0] addr,
    input [31:0] wdata,
    input wr_en,
    input rd_en,
    output [31:0] rdata
    );
    reg [7:0] Mem [255:0];
    assign rdata = rd_en ? Mem[addr]:32'bxxxxxxxx; 
    always @ (posedge clk) begin
        if (wr_en) 
            Mem[addr] <= wdata;
    end
endmodule

Want to assign 4 bytes Mem[3:0] to wdata for write when wr_en flag is 1. more accurately Mem[addr+3: addr]. how can i do this?

1 Answers1

0

Three options:

  1. Use concatenations: {Mem[addr+3],Mem[addr+2],Mem[addr+1],Mem[addr]} <= wdata;

  2. Explicit range selection:

begin
  Mem[addr+3] <= wdata[31:24];
  // other assigments
  Mem[addr] <= wdata[7:0];
end
  1. Or you can Indexing vectors and arrays with +: which allows for(i=0;i<4;i=i+1) Mem[addr+i] <= wdata[i*8 +: 8]
Greg
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