module data_mem(
input clk,
input [31:0] addr,
input [31:0] wdata,
input wr_en,
input rd_en,
output [31:0] rdata
);
reg [7:0] Mem [255:0];
assign rdata = rd_en ? Mem[addr]:32'bxxxxxxxx;
always @ (posedge clk) begin
if (wr_en)
Mem[addr] <= wdata;
end
endmodule
Want to assign 4 bytes Mem[3:0] to wdata for write when wr_en flag is 1. more accurately Mem[addr+3: addr]. how can i do this?