How to write Make rules for *.h files as dependencies

Question

I'm trying to understand how to handle header file dependencies in Make rules. Let me give you a specific example.

I'm building application called myap using GNU Make. It consists of various *.h and *.c files.

Directory inc/ contains defs.h and util.h header files.

Directory src/ contains main.c, cmd.c and win.c files.

Directory obj/ contains all generated object files.

I have multiple applications that need different build options. So I don't want to rely on any implicit rules and would like to specify my own rules for all object files, etc.

I would like to specify the following rules:

Object files depend on specific *.h and *.c files. If any of them change, all object files must be regenerated. However, even though *.h files are part of the prerequisites list, I don't want to pass them to the compiler. I only want to compile *.c files.

Executable myapp depends on specific *.o files. If any of them change, executable file must be regenerated.

So far, the following Makefile with a static pattern rule seems to work correctly:

myapp_inc := inc/defs.h inc/util.h
myapp_src := src/main.c src/cmd.c src/win.c
myapp_obj := $(patsubst src/%.c,obj/%.o,$(myapp_src))
myapp_bin := obj/myapp

.PHONY: all
all:

# Create obj/main.o obj/cmd.o and obj/win.o from various *.c files
# If any *.h files in $(myapp_inc) list change, all objects are regenerated.
# If any *.c files in $(myapp_src) list change, all objects are regenerated.
$(myapp_obj): obj/%.o: src/%.c $(myapp_inc) $(myapp_src)
    gcc -c -o $@ $<

# Create obj/myapp from various *.o files
# If any *.o files in $(myapp_obj) list change, executable is regenerated.
$(myapp_bin): $(myapp_obj)
    gcc -o $@ $^

all: $(myapp_bin)

.PHONY: clean
clean:
    rm -f obj/*

I don't quite understand how Make rules should be written correctly in order to handle such use case. Is the above static pattern rule, the only way that works correctly?

Specifically, I have tried the following combinations, as given in various simple examples on the Internet, and they all failed for various reasons.

This rule causes $< to always pass the name of the first prerequisite, which doesn't work with multiple *.c files:

$(myapp_obj): $(myapp_src) $(myapp_inc)
    gcc -c -o $@ $<

$ make
gcc -c -o obj/main.o src/main.c
gcc -c -o obj/cmd.o src/main.c
gcc -c -o obj/win.o src/main.c
gcc -o obj/myapp obj/main.o obj/cmd.o obj/win.o
/bin/ld: obj/cmd.o: in function `main':
main.c:(.text+0x0): multiple definition of `main'; obj/main.o:main.c:(.text+0x0): first defined here
/bin/ld: obj/win.o: in function `main':
main.c:(.text+0x0): multiple definition of `main'; obj/main.o:main.c:(.text+0x0): first defined here
collect2: error: ld returned 1 exit status
make: *** [Makefile:18: obj/myapp] Error 1

This rule causes $^ to always pass the names of all prerequisites, which fails:

$(myapp_obj): $(myapp_src) $(myapp_inc)
    gcc -c -o $@ $^

$ make
gcc -c -o obj/main.o src/main.c src/cmd.c src/win.c inc/defs.h inc/util.h
gcc: fatal error: cannot specify ‘-o’ with ‘-c’, ‘-S’ or ‘-E’ with multiple files
compilation terminated.
make: *** [Makefile:13: obj/main.o] Error 1

Now I understand the difference between $< and $^ variables, but a lot of documentation is not clear on how they should be used when dealing with a list of multiple *.c and *.h files as prerequisites.

What are the recommended usage pattern for this?

Why is it that when using $< only *.c files get passed to the recipe, but not *.h files? Is Make doing some internal filtering? Is this documented anywhere? Is it possible to modify this behavior for custom suffixes?

Answer 1

Is the above static pattern rule, the only way to make objects depend on *.h and *.c files, but exclude *.h files during compilation?

I don't understand the goal of trying to avoid implicit rules. But in any event, it doesn't matter to the recipe you write whether the rule was implicit or explicit: the same automatic variables are set either way. The $< automatic variable is always the first prerequisite, so if you write your rules such that the first prerequisite is the appropriate .c file then you can always use $< in your recipe to mean the .c file and no other files. All the following will work:

%.o : %.c $(headers)
        gcc -c -o $@ $<
foo.o: foo.c $(headers)
        gcc -c -o $@ $<
foo.o : %.o : %.c $(headers)
        gcc -c -o $@ $<

%.o : %.c
        gcc -c -o $@ $<
$(srcs) : $(headers)

and others.

Does this mean that all of the prerequisites apply, but only those that match the pattern get passed to the recipe?

I don't understand the question, really. The value of variables and the expansion of the recipe happens only AFTER make has decided to run the rule and is not really related (except for some special automatic variables like $?). Once make has decided that the target is out of date and the recipe needs to be run, it will assign the appropriate automatic variables, expand the recipe, then pass the recipe to the shell to be run.

The automatic variables are assigned as described in the manual: $@ is the target, $< is the first prerequisite, $^ is all the prerequisites, etc.

ETA

You still haven't really explained why you don't want to use static pattern rules. They are a perfectly fine and reasonable way to do things.

If you explain what you don't like about static pattern rules, or what you wish you could do differently, then we can probably suggest alternatives that meet those requirements.

Specifically, I have tried the following combinations, as given in various simple examples on the Internet,

$(myapp_obj): $(myapp_src) $(myapp_inc)

Wherever you found this as a recommended example on the Internet, you should immediately delete from any bookmarks as that site doesn't know anything about make.

We see this paradigm at least once a week on SO. I've never really understand why people think it will work: I guess they think make is much more "magical" than it is. Consider, what does the above expand to? Suppose myapp_obj contained foo.o bar.o biz.o and myapp_src contained foo.c bar.c biz.c and myapp_inc contained foo.h bar.h, then make sees:

foo.o bar.o biz.o: foo.c bar.c biz.c foo.h bar.h

I suppose some people think make will intuit that the ".o" files should somehow match up with the ".c" files and will generate a bunch of rules that make that true. That's not what make does. The above line is exactly identical to writing this:

foo.o: foo.c bar.c biz.c foo.h bar.h
bar.o: foo.c bar.c biz.c foo.h bar.h
biz.o: foo.c bar.c biz.c foo.h bar.h

That is, if you have multiple targets make creates one copy of the rule for each target, with the same prerequisites and recipe.

This is obviously not what you want, and that's why none of the examples that try to do things this way can ever work properly.

Why is it that when using $< only *.c files get passed to the recipe, but not *.h files? Is Make doing some internal filtering? Is this documented anywhere? Is it possible to modify this behavior for custom suffixes?

None of that is the case. As I described above, the $< expands to the first prerequisite. That's all. It doesn't matter whether the first prerequisite is a .c file, a .h file, or some other file; whatever it is, $< will be that value. If you write your rule as:

foo.o : foo.c foo.h ; $(CC) -c -o $@ $<

then your compiler will be invoked with foo.c. If you write your rule as:

foo.o : foo.h foo.c ; $(CC) -c -o $@ $<

then your compiler will be invoked with foo.h. There's no magic here.