Sometimes we have to deal with a header file which contains inline code snippets that use macros or variables defined in previous include files. I've met such a problem while trying to make the C object file dependent on the included header files. So I looked it up on stackoverflow and found this but the poster's question is unnecessarily complex so it seems he didn't get the intended answer. So I made a simple example here.
-- main.c
#include <stdio.h>
#define ADDVAL 32
int val;
void set_val(int);
int main()
{
set_val(10);
#include "print_val.h"
return 0;
}
-- set_val.c
extern int val;
void set_val(int a)
{
val += a;
}
-- print_val.h
printf("added value = %d\n",val + ADDVAL);
Of course I can compile and run the program like this.
$cc -c main.c -o main.o
$cc -c set_val.c -o set_val.o
$cc main.o set_val.o -o main
$./main
added value = 42
Now using Makefile.. I made this Makefile.
csrcs := $(wildcard *.c)
cobjs := $(patsubst %.c, %.o, $(csrcs))
main: $(cobjs)
cc $^ -o $@
clean:
\rm -f *.o main
When I do make, it works just fine.
$make
cc -c -o set_val.o set_val.c
cc -c -o main.o main.c
cc set_val.o main.o -o main
But of course the problem is, when I modify print_val.h, it doesn't re-make main.
So I added the header file in the prerequisite list of target 'main' like below.
csrcs := $(wildcard *.c)
cobjs := $(patsubst %.c, %.o, $(csrcs))
main: $(cobjs) print_val.h
cc $^ -o $@
clean:
\rm -f *.o main
Now, after cleaning, if I do make, I see errors.
$ make
cc -c -o set_val.o set_val.c
cc -c -o main.o main.c
cc set_val.o main.o print_val.h -o main
print_val.h:1:8: error: expected declaration specifiers or ??...?? before string constant
1 | printf("added value = %d\n",val + ADDVAL);
| ^~~~~~~~~~~~~~~~~~~~
print_val.h:1:29: error: unknown type name ??val??
1 | printf("added value = %d\n",val + ADDVAL);
| ^~~
make: *** [Makefile:4: main] Error 1
This header file contains execution line and this file cannot be compile by itself.
How should I handle this??
