What is the difference between reg [0:3] mem AND reg [3:0] mem In verilog

Question

The body of this question appears to repeat the question headline; it does not repeat the question headline. The body asked a different question. The body question asks about what happens when the bus index flips from big to little endian on a packed array (vector). The question title asks about packed and unpacked arrays. They are two different questions. The answer was closed based on 'already has an answer here' for packed and unpacked which is not what is asked in the body — Mikef, May 16 '22 at 20:13

Mikef · Answer 1 · 2022-05-16T20:14:21.100

What is the difference between reg [0:3] mem reg [3:0] mem In verilog?

In Verilog a vector is specified as [msb:lsb], where,

msb represents the number of the most significant bit number
lsb represents the least significant bit number

Vectors can be defined using

Little-endian convention(lsb is the smallest bit number)
Big-endian convention(lsb is the largest bit number)

Here is an example where the same value is stored into two vectors as defined in the post.

The lsb is examined to illustrate the difference.

module tb ();
  
  reg [3:0] lsb_is_right;
  reg [0:3] lsb_is_left;
  
  reg lsb_is_right_lsb;
  reg lsb_is_left_lsb;
  
  initial
  begin
  lsb_is_right = 4'b1110;
  lsb_is_left = 4'b1110;
  //
  lsb_is_right_lsb = lsb_is_right[0];
  lsb_is_left_lsb = lsb_is_left[0];
  #1
  $display("lsb_is_right_lsb = %b",lsb_is_right_lsb);
  $display("lsb_is_left_lsb = %b",lsb_is_left_lsb);
  #1;
  $finish;
  end
  
endmodule

Produces:

xcelium> run
lsb_is_right_lsb = 0
lsb_is_left_lsb = 1

What is the difference between reg [0:3] mem AND reg [3:0] mem In verilog

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