It seems like BOOM(Berkeley Out-of-Order Machine) uses PIPT(Physically Indexed Physically Tagged) DCache, but some processors such as intel use VIPT DCache, can anyone tell me why?
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The way Intel uses VIPT, it has the aliasing-avoidance of PIPT but can still check the TLB in parallel with indexing a set. ([Minimum associativity for a PIPT L1 cache to also be VIPT, accessing a set without translating the index to physical](https://stackoverflow.com/q/59279049)) This is an obvious win for L1d load-use latency with no downside (other than limiting L1d size and requiring high associativity to maintain that, but you want it small and fast anyway). L2/L3 is PIPT. IDK why BOOM would not do that; I thought it was pretty normal these days on machines that support virtual memory. – Peter Cordes May 29 '22 at 02:54
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Do you have any links for details on BOOM cache? https://docs.boom-core.org/en/latest/sections/memory-system.html says it's outdated. I've only heard of the project a couple times and don't know where to look for authoritative info other than that. – Peter Cordes May 29 '22 at 03:46