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I have discovered an unexpected problem with a tristate driver developed in VHDL. The behavior of the tristate driver is not understandable in the simulation.

Please have a look at the following code snippet where the signal line_en is set:

process(all)
begin
if (reset = '0') then
    line_en <= '0';
elsif (A /= A_reg) then
    line_en <= '0';
elsif (B_reg /= B) then
    line_en <= '1';
else
    line_en <= line_en;
end if;
end process;

In the simulation it happens now that signal B_reg and B both jump from "0000" to "ZZZZ" at the same time. However, in the transition from "0000" to "ZZZZ" line_en goes to '1' although this should not happen with (B_reg /= B), so the condition must not become true in my opinion.

Attached below a screenshot of the simulation:

Signal Simulation in Vivado

It is for simulation purposes only. Synthesization is not yet desired.

Thanks in advance for any hint where I made a mistake that I can't see myself at the moment. Maybe it's a timing problem because the process itself is not clocked, so it runs asynchronously.

hendrik2k1
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  • `B` and `B_reg` probably change in different simulation steps. You don't see it on the waveform because the two steps happen at the same physical time. But for the simulation algorithm, as they don't change simultaneously, `line_en` is asserted high. And as nothing in your model de-asserts `line_en` when `B` and `B_reg` finally take the same value, it stays high. – Renaud Pacalet Aug 04 '22 at 09:58
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    Add `report "B=" & to_string(B) & ", B_reg=" & to_string(B_reg);` at the beginning of your process and see what really happens. – Renaud Pacalet Aug 04 '22 at 10:02
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    Add all the signals as well as the value produced by the relational operators which will demonstrate order of all simulation cycles including delta cycles. Signal assignments are queued and updates occur earlier in a simulation cycle than processes resume, execute and subsequently suspend, the beginning of the next simulation cycle at the earliest. Delta cycles and signal updates emulate concurrency and you've implied a latch with combinational enables (which won't synthesize reliably, nor will evaluating 'Z's relationally). – user16145658 Aug 04 '22 at 10:23
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    This implements a (glitch-prone, as you found) latch, not a tri-state. (Also, comparisons with 'Z' won't work in reality) –  Aug 04 '22 at 10:45
  • Without a [mcve] your readers can only show you [the problem can be caused by a delta delay in assigning B_reg](https://i.stack.imgur.com/ccvbk.jpg). – user16145658 Aug 05 '22 at 01:36

1 Answers1

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The comments are right and seemingly pointing in the right direction. It is caused from delta delay (i.e. simulation steps) when simulation is running. By reconsideration of the above logic design and how Vivado integrated simulator works, I came to the conclusion that creating an asynchronous logic can cause flaws or behavior that is not desired or deviates from a synthesized design.

It is for simulation purposes only. I'm aware that comparison with Z won't work in synthesized logic. I added this to the opening question.

hendrik2k1
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