0

I'm doing an exercise about the MIPS pipeline with the following characteristics:

  • Branches and Branch targets are calculated in the E-stage.

-There is forward logic from the output to the input of the E-stage.

  • You can read an operand from the register file only the cycle after it has been written to it.

This is the code I'm making the diagram for, I don't understand why there are two stalls (X) on the third instruction. Should it not be F X X X D given that the forwarding is from WB to D?

The mips implementation is here

The mips code is here.

The diagram is here

Erik Eidt
  • 23,049
  • 2
  • 29
  • 53
Begin
  • 13
  • 4
  • Neither the assembly/machine code sequence nor the dependencies (which can be determined from the code sequence) ate shown, so question is very hard to reason over. Perhaps intended to include that? – Erik Eidt Aug 11 '22 at 20:58
  • 1
    It is unusual that the registers cannot be read until rhe cycle after being written, more usually they can be read in the same cycle written. Most articles and posts will take that assumption. – Erik Eidt Aug 11 '22 at 21:17
  • @ErikEidt This is for a course exercise, maybe that's why it deviates. The mips code is included in the blue code link, I made it now more clear to see – Begin Aug 11 '22 at 21:29
  • I can't tell if your theoretical implementation has forwarding or not.if yes, should forward from M to E with 1 cycle stall. If no, should delay D until after W as you say. – Erik Eidt Aug 12 '22 at 13:31
  • @ErikEidt I added a picture of the MIPS implementation, there is no forwarding from M to E in this theoretical one :( – Begin Aug 12 '22 at 16:41
  • Ok, so given that block diagrsm and the table of cycles/stages, it is forwarding from W to E, so doesnt have to wait that one extra cycle to redo D. FDXXEMW makes sense then. – Erik Eidt Aug 12 '22 at 18:33
  • from the block diagram, I understood that you can forward from W to D. What am I missing seeing in the diagram that allows it to forward from W to D? – Begin Aug 12 '22 at 18:49
  • Its the forward from W to E that is being used there. Yes, it can forward from W to D, but in comparison, W to E saves 2 cycles so is a better choice. If it had M to E that would be even better there, saving another cycle. – Erik Eidt Aug 12 '22 at 19:34
  • 1
    We wouldnt necessarily even call W to D "forwarding" because that is just a normal path thru the register file. Forwarding is a mechanism of overriding a stale value obtained during D, with the proper value from a subsequent execution stage. There's no stale value, no override in W to D. – Erik Eidt Aug 12 '22 at 19:38
  • The W stage writes the register file and D reads the register file. Given that a D read in the next cycle can read what was written in the prior cycle W, a "forward" from W to D doesnt really make any sense, so I think that path is just illustrative of passing data through the register file. – Erik Eidt Aug 12 '22 at 23:31
  • Fun fact: in early commercial MIPS implementations, 1 branch-delay slot was sufficient to hide branch latency thanks to some half-cycle trickery in forwarding from EX to IF. [How does MIPS I handle branching on the previous ALU instruction without stalling?](https://stackoverflow.com/q/56586551) – Peter Cordes Aug 12 '22 at 23:52
  • @PeterCordes Interesting, I never knew! – Begin Aug 13 '22 at 18:40
  • I would recommend a wonderful youtube video: https://www.youtube.com/watch?v=EW9vtuthFJY – A. Herlas Oct 12 '22 at 11:22

0 Answers0