Verilog indexing through a vector by 4 bits

Question

Please excuse my novice question.

I have a vector:

wire [WIDTH-1:0] data_in;

and would like to obtain only the bits highlighted below:

|63|....|31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|

So basically, skip 4LSB bits, then capture the following 8 bits, then skip 4 bits ..

The current code:

localparam WIDTH = 64;
wire [WIDTH*64-1:0] data_in;    
assign data_in[WIDTH*0+:WIDTH] = data_out;

I would like to know how to use this answer https://stackoverflow.com/a/18068296/20013745 to iterate through the bits as per above.

Many thanks

The value 14 is skipped in the counting. The count shown goes 15|13| — Mikef, Sep 16 '22 at 16:11
Now the count has five skip bits (12,13,14,15,16) between the two keep sections. Should be four skip bits and the eight keep bits just to the left of these should move down. If the count is corrected its easier to see the pattern for the LHS of the keep bits: 12*1 -1, then 12*2 -1, then 12*3 -1. then 12*4 -1.... — Mikef, Sep 16 '22 at 16:49

score 0 · Answer 1 · answered Sep 16 '22 at 17:31

There are no syntax shortcuts for selecting non-contiguous bits in a single expression. You need to use a for loop either by creating a function containing it to use in the continuous assignment, or you can change the wire to a variable and use an always block.

integer i;
always @*
  for(i = 0;i<64/12;i=i+1);
      data_out[i*8+:8] = data_in[(4+i*12)+:8];

Verilog indexing through a vector by 4 bits

1 Answers1