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We have a server with Intel(R) Xeon(R) Gold 6338N CPU @ 2.20GHz.

For this server the L1, L2, L3 caches seem not enabled...

Is there a way to check the CPU registers with msr tools (rdmsr/wrmsr) on Linux to see if the caches are enabled and optionally to enable/disable them ?

What are the relevant registers?

The problem is.... I found only relevant information on the CPU register CR0 for the CD bit, but the register CR0 can be accessed only from ring 0 (i.e. only from the kernel), instead my question is if there is the possibility to access registers relevant to the caches from ring 3 (i.e. user space).

Rachid K.
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fstrati70
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  • I think that linked duplicate ([How can the L1, L2, L3 CPU caches be turned off on modern x86/amd64 chips?](https://stackoverflow.com/q/48360238)) covers Intel's documentation on the MSR numbers; it shows asm to disable cache (after using `wbinvd` to drain it, not 100% sure that's necessary). The same MSR could be read. I might have been a bit hasty since you're asking about using msr-tools from the command line, as well as which MSRs are relevant. – Peter Cordes Sep 23 '22 at 09:24
  • I think my question is still relevant and not a duplicate... I found that info enable/disable for the caches is in the cpu register cr0, but that can be accessed only by the kernel as it is in ring 0... and I didn't found any viable alternative from ring 3.... – fstrati70 Sep 23 '22 at 14:44
  • Well obviously not from ring3 alone; msr-tools makes a system call to ask the kernel (ring 0) to run a `wrmsr` or `rdmsr` instruction (e.g. read or write on `/dev/cpu/*/msr`). A similar kernel module is needed to let user-space ask for it to modify bits in control registers. – Peter Cordes Sep 23 '22 at 21:55

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