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I'm new to VHDL. I learned that the sequential statement under the process is always sequential. But in my snippet below, Q will have the old temp value. It seems that it contradicts to the sequential statements since Q will not update to the newest temp value.

process (CLK)
  begin
    if(rising_edge(CLK)) then
      temp <= D;
      Q <= temp;
    end if;
  end
process
helloword
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  • Welcome to StackOverflow! Please add a [mre], because we cannot see what `temp` is exactly. What does your beginner's book say about assignments to signals in a process? – the busybee Oct 24 '22 at 07:23
  • You code has syntax errors. First off `endif` is not a keywords in vhdl, you need `end if`. Secondly, the process contains no wait statements and no sensitivity list, so it will loop forever at time 0. – Tricky Oct 24 '22 at 08:34
  • thank your point out these errors – helloword Oct 24 '22 at 18:57
  • As shown in the process statement temp and Q infer two flip flops as a shift register, both operating on the same clock edge event and the output of first as the input to the second. – user16145658 Oct 24 '22 at 19:34
  • https://stackoverflow.com/questions/13954193/is-process-in-vhdl-reentrant/13956532#13956532 –  Oct 26 '22 at 20:08

1 Answers1

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The signals temp and Q will be two separate flip-flops. The value of a flip-flop only updates on each rising edge of CLK.
Note that it is not like programming. You are essentially connecting flip-flops, but the their values will not be updated until the next rising edge. With that, the order of the assignements within the process does not matter. (as long as you have only one assignement for each signal)

The scematic in hardware will look something like this. Note, each flip-flop will only update on the next rising edge.

------      -----
|temp| ---> | Q |
------      -----

If you need a different behavour (where temp is not a separate flip-flop), temp needs to be a variable instead of a signal.
I hope that helps.

Andi R
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  • thank you for your answer. What confuses me is that both signals temp and Q are updated in the process, it seems that they work concurrently instead of sequentially. But the book says all the statements within the process are sequential. – helloword Oct 24 '22 at 19:00
  • Signal updates are scheduled for the current simulation time (no after clause) or a future simulation time. All signals are updated in an earlier part of a simulation cycle than when any process is yet to resume execution and subsequently suspend. The purpose is to emulate signal concurrency using delta cycles before simulation time advances as opposed to a requirement to order variable assignments. Note here the process evaluates the clock edge prior to temp or Q assignment, a behavior signifying sequential storage elements (flip flops). – user16145658 Oct 24 '22 at 19:56
  • I am not sure what your book means exactly with the statements beeing sequential. Generally VHDL does work concurrently. However, if you would have multiple assignements to `Q` (withing one process), one could talk about sequential. For example in your process: First you assign `Q<='0'` (this is also called a default assignement) and then (maybe under some condition) you assign `Q <= temp`. Now only the last assignement in the process defines the value of `Q` in the next clock cycle. The behavour would change if you assign `Q<='0'` at the end of the process istead of the beginning. – Andi R Oct 25 '22 at 07:46