Does GCC generate wrong assembly code for the "jal" instruction of riscv?

Question

generate jal instruction for riscv gets the unexpected code

I have a riscv assembly code in test_jal.s:

jal a0, 42

And I compile it with

riscv64-linux-gnu-gcc -c -Wl,-Ttext=0x0 -nostdlib -mno-relax -o test_jal test_jal.s

Then I generate the raw riscv binary by

riscv64-linux-gnu-objcopy -O binary test_jal test_jal.bin

I use hexdump -C test_jal.bin to generate its hex code:

6F 05 00 00

Then I use riscv64-linux-gnu-objdump to disasm it. I got

jal     a0,0x0

May I do something wrong?

System: WSL ubuntu 22.04 gcc verison: 9.3.0

what do you do with `a0` after? Since you push this through the compiler (instead of just the assembler), I could imagine a compiler pass removing an "effectless" instruction. — Marcus Müller, Nov 06 '22 at 10:22
do nothing, Im just testing my emulator, so you mean the compiler do this intentionally? what can I do to disable this sideeffect? — Euphonious, Nov 06 '22 at 10:31
try with `-O0` to disable optimizations. or use `a0` afterwards. — Marcus Müller, Nov 06 '22 at 10:31
nowhere, the whole .s file only contains that one instruction. I test -O0 it doesn't work — Euphonious, Nov 06 '22 at 10:38
RISC V doesnt have absolute addressing for`jal` so it will generate some relocation for that, which perhaps is not being dumped or otherwise lost. — Erik Eidt, Nov 06 '22 at 15:00
See also https://stackoverflow.com/a/72924146/471129, using absolute address with branch instruction. — Erik Eidt, Nov 06 '22 at 15:07
but `jal` is PC-relative, so jal a0, 42 means set pc to pc+42, that should not be the absolute addressing? — Euphonious, Nov 07 '22 at 13:24

score 0 · Answer 1 · answered May 10 '23 at 10:28

Probably the assembler convert 42 to zero since there's no place to jump basically. Try a longer function like:

.global main

.data
    msg: .string "Hello World!"
.text
   main:    
       jal  ra, function
    
       li   a7, 93
       li   a0, 0
       ecall

   function:
      la t0, msg
    
      li a7, 4
      mv a0, t0
      ecall
    
      ret

This is an example done for Rars Emulator

Does GCC generate wrong assembly code for the "jal" instruction of riscv?

1 Answers1