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I'm studying RISC-V (32-bit) computer architechture and I'm having a hard time understanding this type of data hazard. Suppose that we have instructions like this:

or x4, x3, x4

bne x4, x4, error (not taken)

addi x2, x0, 1060

sw x4, 0(x2)

Suppose that the format of sw instruction is sw rs2, rs1(12-bit immediate). At the sw instruction, we get the value of rs2 (x4) in the decoding stage, but the value of x4 changes by the "or x4, x3, x4" instruction. As far as I know, the value of the register is updated at the clock right after the writeback stage. So at the decoding stage of the "sw" instruction, the data at the register file is not updated. Therefore a data hazard happens.

But I learned that data hazard only happens between ID/EX stage and EX/MEM, MEM/WB stage, not after the WB stage. How do we deal with this data hazard? Or, am I misunderstanding something? Any help is appreciated!

Hypernova
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  • @ErikEidt It did. Then if I'm implementing the RISC-V CPU in Verilog with 5 stages, then should I manually add forwarding in that case? – Hypernova Nov 21 '22 at 16:31
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    If it needs it, but it probably doesn't. As the textbooks by Patterson and Hennessey say: "As is the case for many implementations of register files, we have no data hazard in this case.". Since the circuitry for the write and the read are both enabled at the same time, we would expect the value read to change quickly from the stale register-held value to the newly-written value as a simple matter of settling by the end of the cycle. – Erik Eidt Nov 21 '22 at 16:40
  • @ErikEidt Thanks!! I succeed implementing it thanks to you – Hypernova Nov 22 '22 at 05:46

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