Low pass FIR FILTER

Question

I was assign to make low pass fir filter. this is what is assign asking me:

Write a module that will act as a low-pass FIR filter. Input and output signals should be 16-bit and signed. Add a sample clock input and another faster clock to keep things running. Test the operation in a simulation by generating a square signal at the input and observing the output signal. Show your implementation and simulation results in the presentation.

this is how my current code stands:

module Fir_filter(
    input clk, //ura
    input rst, //reset if high
    input signed [15:0] vhodni_signal, //16 bitni predznačen vhodni signal
    output signed [15:0] izhodni_signal, // izhod signal, kateri bo tudi rezultat
    );
    reg signed [35:0] vmesni_rezultati; // pomnožen vhod + signal
    wire  signed [19:0] A[0:8]; // register namenjen koeficientom
    reg signed [8:0] rezultat;
    reg signed [15:0] vhodni_signal_shiftan;
    
        assign A0 = -62;
        assign A1 = 396;
        assign A2 = 5020;
        assign A3 = 14346;
        assign A4 = 19660;
        assign A5 = 14346;
        assign A6 = 5020;
        assign A7 = 396;
        assign A8 = -62;

    always @(posedge clk)
    begin
       vmesni_rezultati = A0 * vhodni_signal[0] + A1 * vhodni_signal[1] + A2 * vhodni_signal[2] + A3 * vhodni_signal[3] + A4 * vhodni_signal[4] + A5 * vhodni_signal[5] + A6 * vhodni_signal[6] + A7 * vhodni_signal[7] + A8 * vhodni_signal[8];
        rezultat[0] = vmesni_rezultati[31:16];
    
         
        end
    
     endmodule

keep in mind that assign A0-A8 is clearley for fir coeficients. I did use fir filter calculator to get these numbers. numbers are multiplyed with 65536 and rounded

So what is my question. I have taken the input signal multiplyed it with coeficents and stored it in rezultat. now i have to do that 8 more times to multiply whole input signal.(in my logic i currently did only 1 sample.) i dont know how to take next sample of input signal and multiply it with coeficients. If anyone could do me a big favour i would ask if you can write code for simulation.

i am using vivado 2021.1-Verliog language.

i have reported that in previous question.

Answer 1

The posted code is attempting to multiply individual bits of one sample * coefficient.
That is not how an FIR works.
An FIR multiplies a whole sample by a coefficient, then another whole sample by a different coefficient then sums up the products.

The design needs a 9 sample shift register to implement 9 FIR delays/taps.
Each tap gets multiplied by a coefficient and all the products are summed to form the output.

module Fir_filter(
  input  clk,
  input  rst, 
  input      signed [15:0] input_sample,
  output reg signed [35:0] filter_output
);

  reg signed [15:0] filter_taps[8:0];

  reg signed [15:0] A0,A1,A2,A3,A4,A5,A6,A7,A8;
  
  assign A0 = -62;
  assign A1 = 396;
  assign A2 = 5020;
  assign A3 = 14346;
  assign A4 = 19660;
  assign A5 = 14346;
  assign A6 = 5020;
  assign A7 = 396;
  assign A8 = -62;

integer i;
always @(posedge clk)
  if(rst) 

    for(i = 0;i < 9;i=i+1) 
      filter_taps[i] <= 0;

  end
  else begin :sync_proc_block

    // input drives first tap
    filter_taps[0] <= input_sample;

    // shift reg
    for(i = 1; i < 9; i=i+1) 
      filter_taps[i] <= filter_taps[i - 1];
        
  end :sync_proc_block

always @ (*) 
  filter_output =
    A0 * filter_taps[0] +
      A1 * filter_taps[1] +
        A2 * filter_taps[2] +
          A3 * filter_taps[3] +
            A4 * filter_taps[4] +
              A5 * filter_taps[5] +
                A6 * filter_taps[6] +
                  A7 * filter_taps[7] +
                    A8 * filter_taps[8];

endmodule

See this answer for how to write a basic testbench.
Can anyone help me to create a Verilog testbench?