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In the middle of this page (https://github.com/ultraembedded/riscv), there is a block diagram about the core, I really do not know what is TCM doing in the same block with the Icache ? Is it an optional thing to be inside the CPU ? enter image description here

Neom5
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2 Answers2

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Some embedded systems provide dedicated memory for code and/or for data.  On some of these systems, Tightly-Coupled Memory serves as a replacement for the (instruction) cache, while on other such systems this memory is in addition to and along side a cache, applying to a certain portion of the address space.  This dedicated memory may be on the chip of the processor.

This memory could be some kind of ROM or other memory that is initialized somehow prior to boot.  In any case, TCM typically isn't backed by main memory, so doesn't suffer cache misses and the associated circuitry, usually also has high performance, like a cache when a hit occurs.

Some systems refer to this as Instruction Tightly Integrated Memory, ITIM, or Data Tightly Integrated Memory, DTIM.

When a system uses ITIM or DTIM, it performs more like a Harvard architecture than the Modified Harvard architecture of laptops and desktops.

Erik Eidt
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  • It says that ITIM "provide low-latency access to instruction memory", however since it is a kind of ROM, would not be slower ? Also if the core is implemented with icache/TCM as the above RISCV, how would the CPU decide to take the instructions from ? – Neom5 Jan 19 '23 at 04:58
  • By address range, but I don't know how it is configured. – Erik Eidt Jan 19 '23 at 06:21
  • I see, So this CPU actually working with both icache and TCM. But when does it need to access icache and when does it need to access TCM ? Also, From the link I provided, it says : (0x0000_0000 - 0x0000_ffff 64KB TCM Memory) which is the address range of TCM, and MEM_CACHE_ADDR_MIN = 0 MEM_CACHE_ADDR_MAX = 32'hffffffff ..... It seems that cache (it did not specify instruction or data ) has covered the full range of addresses including TCM !! It is confusing a bit to me – Neom5 Jan 19 '23 at 07:56
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The cache has no address space. CPU does not ask for data from the cache, it just asks for a data, then the memory controller first checks the cache if the data is present in the cache. If it is in the cache, data is fetched, if not then the controller checks the RAM. All processor does is ask for data, it does not care where the data came from. In the case of TCM, the CPU can directly write data to TCM and ask data from TCM since it has a specific address. Think of TCM as a RAM that is close to the CPU.

ALPEREN K
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