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RISC-V assembly features two mnemonics jump and tail, both of which perform an unconditional jump to another symbol. What is the difference between the two?

Both are pseudo-instructions that get expanded by the assembler but the difference is unclear.

David Monniaux
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    did you read the [spec](https://riscv.org/technical/specifications/)? There's no `tail` instruction, only pseudoinstruction. And there's `j`, not `jump`. Everything is explained in the spec – phuclv Feb 03 '23 at 06:47
  • @phuclv, there's no actual `j` either — that's a pseudo instruction for a degenerate `jal` that (doesn't) captures the pc into `x0`. – Erik Eidt Feb 03 '23 at 15:40
  • Does this answer your question? [How do I write NOT Operation for the Risc-V (Assembly Language)?](https://stackoverflow.com/questions/65006052/how-do-i-write-not-operation-for-the-risc-v-assembly-language) – Erik Eidt Feb 03 '23 at 15:43
  • This is why I said "mnemonic" and not "instruction". Furthermore, the GNU assembler does have a `jump` pseudo instruction – David Monniaux Feb 03 '23 at 20:37

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It seems that the GNU assembler understands tail XXX as

  auipc x6, (something appropriate for XXX)
  jr x6, (something appropriate for XXX)

whereas jump XXX, RR is understood as

  auipc RR, (something appropriate for XXX)
  jr RR, (something appropriate for XXX)

In short, jump lets you choose the temporary register that gets clobbered by the computation of the destination.

In any case, the GNU linker removes the auipc if the target is close enough.

David Monniaux
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  • Can you cite the (presumably GCC/GAS) documentation for these mnemonics? (Pretty sure linker "relaxation" is responsible for removing the `auipc` when not necessary.) – Erik Eidt Feb 03 '23 at 23:46
  • If I had documentation about that I would not have to ask on StackOverflow. I saw a compiler emitting `jump`, other emitting `tail`, and both accepted by the assembler. I would specially like to know about possible differences in relocation. – David Monniaux Feb 04 '23 at 08:02
  • https://www.sifive.com/blog/all-aboard-part-3-linker-relaxation-in-riscv-toolchain – Erik Eidt Feb 04 '23 at 15:05