Context:
An SPI bus is being used to communicate the iMX8 with an FPGA. After some configuration commands, the FPGA begins to fill a memory. When this memory is full, the iMX8 is notified and sends a command to read data from the FPGA. At that point, the FPGA should start sending the data.
The problem:
The problem is that, in the middle of the transmission (while the CS is LOW), the SCLK gets stuck in HIGH and the transmission is extended by "x" microseconds/milliseconds (sometimes more, sometimes less).
Different transmissions get stuck different amount of time.
Does someone know where can be this problem coming from? Can it be some issue with the SPI buffers?
I use spi_ioc_transfer struct in order to sends commands from the iMX8 to the FPGA via ioctl system call.
int transfer16(int fd, uint16_t *tx, uint16_t *rx, uint32_t len)
{
int ret;
errno=0;
struct spi_ioc_transfer tr = {
.tx_buf = (__u64)tx,
.rx_buf = (__u64)rx,
.len = len,
.delay_usecs = 1,
.speed_hz = spi_speed,
.bits_per_word = 16,
};
ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);
if (ret< 0){
printf("SPI IOCTL ret(%d), error(%d) %s\n", ret, errno, strerror(errno));
}
return ret;
}
