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How much should I add when using "jal" in RISC-V and 1 word is 8-byte?

jal x10 foo //x10 has O

As I know, "jal" instruction place foo address in PC(program counter, x2) so procedure can jump to foo, and in parallel, place (PC + 4) value in x10 (in this code) as return address to excute next procedure after return.

What I'm curious about is, using RISC-V ISA and 1 word is 8-byte, which number should I add, 4 or 8?

Likeas, when 1 word is 8-byte, how should I set offset?

For example,

f = g + A[8] (f, g are placed in x5, x6, respectively)

(base address of A[] is placed in x10)

add x5, x6, 64(x10) is it right?

I assume it's correct because index * word = 8 * 8(byte) = 64

I studied in 1 word = 4-byte architecture so all I know is

A[8] (base address is placed in x10) is same as 2(x10) <- True.

If in 1 word = 8-byte architecture,

and if A[8] is same as 1(x10), it means 1 word is automatically considered as 8-byte, then why there exists ld (load doubleword) instruction? I guess it's false.

pedro1798
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    Not exactly sure what you mean, but instructions are 4 bytes hence the `PC + 4` which is quite clear. I don't understand what you are trying to do with the `add`. – Jester Apr 14 '23 at 19:38
  • Ah add was just another example, but now I think 4 in (PC + 4) and offset are different. What I confuse is if when I use 4-byte architecture and 8-byte architecture, offset value and 4 in PC + 4 changes or not, because 1 word is changed . – pedro1798 Apr 14 '23 at 19:49
  • It does not change because instructions are still 4 bytes even in riscv64. – Jester Apr 14 '23 at 19:50
  • Thanks a lot!!!!! I searched it for hours but I couldn't find answer. – pedro1798 Apr 14 '23 at 19:56
  • `words` are data, so they don't affect instruction sizes. They do affect register sizes, but since they don't affect instruction sizes, then the PC is simply wider, but the `jal` is the same size, so the same value is added. – Erik Eidt Apr 14 '23 at 20:18
  • See also https://stackoverflow.com/questions/62807066/riscv32-vs-riscv64/62819417#62819417 – Erik Eidt Apr 14 '23 at 20:19
  • Thanks, I read that page, I'm now understand 32-bit and 64-bit differ in register size, not instruction size. ahhhhh I get it. even though using 64-bit architecture, A[8] is still 32(x10).. Thanks again. It became clear. – pedro1798 Apr 14 '23 at 20:33
  • Yeah, the 64-bit processor has one more naturally supported data size, though a language like C determines sizes of scalars and/or array elements, so a 32-bit machine can use 64-bit scalars (or array elements) just needs more instructions for add/mult etc.., since that 64-bit size isn't as well supported on those processors. – Erik Eidt Apr 14 '23 at 22:44

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