verilog for numbered signals and passed in string in instance name

Question

First, I want to instantiate a bunch of modules using genvar in verilog where each instance basically contains what the value of the index is, to make them have different names so I can tie them to an 8 bit bus, one buffer per bit. Since I want to stay verilog compatible, I cannot have 2D variables in the instantiation of the module.

this is what I want to do, somehow get the i variable into the name of the signal. Not sure if this is even possible.

genvar i;
for (i=0; i<100; i=i+1)
begin
  my_module My_mod_"i"
     (
     .A (input_"i"_value),     //   example  input_1_value[31:0] for i=1
     .I (i),                   //   0 to 99
     .O (output_"i"_value)     //   example  output_1_value[31:0] for i=1
     );
end

so I synthesize:

my_module my_mod_0
     (
     .A (input_0_value),       //   input_0_value[31:0] for i=0
     .I (i),                   //   0 to 99
     .O (output_0_value)       //   output_0_value[31:0] for i=0
     );

my_module my_mod_1
     (
     .A (input_1_value),       //   input_1_value[31:0] for i=1
     .I (i),                   //   0 to 99
     .O (output_1_value)       //   output_1_value[31:0] for i=1
     );

Any suggestions??

Haven't been able to code anything yet that looks credible.

Yes. Verilog IEEE HARDWARE DESCRIPTION LANGUAGE Std 1364-2005, section 4.9.2 reg and variable arrays says 'Arrays for all variables types (reg, integer, time, real, realtime) shall be possible.' — Mikef, Apr 15 '23 at 00:39
building names like `input_0_value` in *genblocks* is **impossible** in verilog. Your syntax with `"i"` is illegal. There is no need for it in instance name. Use arrays for ports instead. — Serge, Apr 15 '23 at 13:42

score 0 · Answer 1 · answered Apr 20 '23 at 17:14

Verilog does not support using a genvar in the middle of an identifier.

For a pure Verilog solution, you need to concatenate all the related signals or create an intermediated two dimensional array.

Example of slicing concatenated signals (Refs: What is `+:` and `-:`? , Indexing vectors and arrays with +:)

genvar i;
for (i=0; i<100; i=i+1) begin : gen_my_module
  my_module My_mod
     (
     .A (input_value[i*32 +: 32]),
     .I (i),                   //   0 to 99
     .O (output_value[i*32 +: 32])
     );
end

An alternative solution is to create a script to generate the code for you. You can have the code generated by your preferred programming language, then use an `include statement in your verilog file. Or you can go with an embedded route:

Emacs has a build-in verilog-mode plug-in using LISP : latest version https://github.com/veripool/verilog-mode
Perl had EP3 : http://metacpan.org/pod/Text::EP3::Verilog
Ruby has eRuby : http://www.tutorialspoint.com/ruby/eruby.htm
Python had prepro but I can no longer find it. An equivalent probably exists
I'm sure something like it exists for other languages to. Such as Tcl, JavaScript, C, etc.

Concept is the same, just a difference in embedded language and tool used for conversion.

Example using EP3:

@perl_begin
  foreach my $idx (0..100) {
    printf "my_module My_mod_%0d",idx;
    printf "   (";
    printf "   .A (input_"i"_value),",$idx;
    printf "   .I (%0d),";,$idx
    printf "   .O (output_%0d_value)",$idx;
    printf "   );";
  }
@perl_end

verilog for numbered signals and passed in string in instance name

1 Answers1