If each CPU cache line has 64 bytes, one data has 8 bytes. When the data's physical address is at block offset 60, i.e., it would be stored across 2 cache lines.
+---------+
| data |
+-------------------------------+-------------------------------+
| cache line 1 | cache line 2 |
+-------------------------------+-------------------------------+
64 bytes 64 bytes
How will cache load & store the data? If there is a load instruction to fetch data: ld rd,offset(rs1)
, will these 2 cache lines get hit together?
Or the compiler is smart enough so the load instruction will be broken into 2 instructions to load 4 bytes data at each time?