I use mmio axi4 for data store, the rtl simulation in vcs is ok, but in spike, I got error like this:
(base) ubuntu@ubuntu:~/riscv/software$ spike math.elf
Access exception occurred while loading payload math.elf:
Memory address 0x60000000 is invalid
This is the device tree dumped by spike --dump-dts command:
/dts-v1/;
/ {
#address-cells = <2>;
#size-cells = <2>;
compatible = "ucbbar,spike-bare-dev";
model = "ucbbar,spike-bare";
chosen {
stdout-path = &SERIAL0;
bootargs = "console=ttyS0 earlycon";
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <10000000>;
CPU0: cpu@0 {
device_type = "cpu";
reg = <0>;
status = "okay";
compatible = "riscv";
riscv,isa = "rv64imafdc";
mmu-type = "riscv,sv57";
riscv,pmpregions = <16>;
riscv,pmpgranularity = <4>;
clock-frequency = <1000000000>;
CPU0_intc: interrupt-controller {
#address-cells = <2>;
#interrupt-cells = <1>;
interrupt-controller;
compatible = "riscv,cpu-intc";
};
};
};
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x80000000>;
};
soc {
#address-cells = <2>;
#size-cells = <2>;
compatible = "ucbbar,spike-bare-soc", "simple-bus";
ranges;
clint@2000000 {
compatible = "riscv,clint0";
interrupts-extended = <&CPU0_intc 3 &CPU0_intc 7 >;
reg = <0x0 0x2000000 0x0 0xc0000>;
};
PLIC: plic@c000000 {
compatible = "riscv,plic0";
#address-cells = <2>;
interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9 >;
reg = <0x0 0xc000000 0x0 0x1000000>;
riscv,ndev = <0x1f>;
riscv,max-priority = <0xf>;
#interrupt-cells = <1>;
interrupt-controller;
};
SERIAL0: ns16550@10000000 {
compatible = "ns16550a";
clock-frequency = <10000000>;
interrupt-parent = <&PLIC>;
interrupts = <1>;
reg = <0x0 0x10000000 0x0 0x100>;
reg-shift = <0x0>;
reg-io-width = <0x1>;
};
};
htif {
compatible = "ucb,htif0";
};
};
This is the device tree generated when compile verilog in rocket chip:
/dts-v1/;
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "freechips,rocketchip-unknown-dev";
model = "freechips,rocketchip-unknown";
L15: cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <1000000>;
L4: cpu@0 {
clock-frequency = <0>;
compatible = "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <16384>;
d-tlb-sets = <1>;
d-tlb-size = <32>;
device_type = "cpu";
hardware-exec-breakpoint-count = <1>;
i-cache-block-size = <64>;
i-cache-sets = <64>;
i-cache-size = <16384>;
i-tlb-sets = <1>;
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
next-level-cache = <&L10>;
reg = <0x0>;
riscv,isa = "rv64imafdcZicsr_Zifencei_Zihpm_Xrocket";
riscv,pmpgranularity = <4>;
riscv,pmpregions = <8>;
status = "okay";
timebase-frequency = <1000000>;
tlb-split;
L2: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
};
L10: memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x10000000>;
};
L14: soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "freechips,rocketchip-unknown-soc", "simple-bus";
ranges;
L6: clint@2000000 {
compatible = "riscv,clint0";
interrupts-extended = <&L2 3 &L2 7>;
reg = <0x2000000 0x10000>;
reg-names = "control";
};
L7: debug-controller@0 {
compatible = "sifive,debug-013", "riscv,debug-013";
debug-attach = "dmi";
interrupts-extended = <&L2 65535>;
reg = <0x0 0x1000>;
reg-names = "control";
};
L1: error-device@3000 {
compatible = "sifive,error0";
reg = <0x3000 0x1000>;
};
L9: external-interrupts {
interrupt-parent = <&L5>;
interrupts = <1 2>;
};
L5: interrupt-controller@c000000 {
#interrupt-cells = <1>;
compatible = "riscv,plic0";
interrupt-controller;
interrupts-extended = <&L2 11 &L2 9>;
reg = <0xc000000 0x4000000>;
reg-names = "control";
riscv,max-priority = <3>;
riscv,ndev = <2>;
};
L11: mmio-port-axi4@60000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges = <0x60000000 0x60000000 0x20000000>;
};
L12: rom@10000 {
compatible = "sifive,rom0";
reg = <0x10000 0x10000>;
reg-names = "mem";
};
L0: subsystem_pbus_clock {
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-output-names = "subsystem_pbus_clock";
compatible = "fixed-clock";
};
};
};
Generated Address Map
0 - 1000 ARWX debug-controller@0
3000 - 4000 ARWX error-device@3000
10000 - 20000 R X rom@10000
2000000 - 2010000 ARW clint@2000000
c000000 - 10000000 ARW interrupt-controller@c000000
60000000 - 80000000 RWX mmio-port-axi4@60000000
80000000 - 90000000 RWXC memory@80000000
I also tried command like this: spike --dts=./device.dtb math.elf, but it's not working.
