Have a look at the Verilog code below:
module first(input a, input b, output c)
assign c= a&b;
endmodule
And then we call this module into another module like as below
module second(input d, input e, output f)
first instance_name (.a(d), .b(e), .c(f));
endmodule
As we can clearly see that which port is connected with which port. While calling a function in C++, its always a danger that we will miss a port and place some unwanted variable there.
Is there any similar way of doing things in C++?