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Recently I was learning 'Computer Organization and Design RISC-V' book by David A. Patterson, and was stuck by some questions. Why RISC-V 'J-immediate' put imm[11] in inst[20] instead of inst[24]?

Is it related with detailed circuit design, if so, Could someone offer reference link or better with more helpful explanation based on the specific circuit design?

I found valuable resources answering related questions about (S)B-immediate and also read some references like page 17 in official doc volume 1.

zg c
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  • How would `inst[24]` make any sense as the location for `imm[11]`? That's in the middle of the `imm[10:1]` field, so it would make it not route the same as I-type instructions. If anything, `inst[31]` would make sense, and put `imm[20]` into `inst[20]`, where it would be contiguous with the `imm[19:12]` field. But RISC-V always puts the most-significant bit of any immediate in `inst[31]` to allow a shorter critical path for sign-extension, as explained in quotes from the architects in the Q&A you already linked. So that's why they swap `imm[20]` and `11` – Peter Cordes May 27 '23 at 13:57
  • Thanks for your comment. 1- After reading the official doc p17 detailedly, the 'maximize overlap' is similar to your 'in the middle of'. (Sorry for asking one newbie question without reading official doc more carefully) 2- Although I am not familiar with hardware (which I will learn more detailedly if learning software with bottlenecks) as what I do with software, I can get some meaning about that the convention will simplify hardware design by generalization. – zg c May 31 '23 at 10:41

1 Answers1

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A short answer is it has to go somewhere, and the longer answer is that with that overall arrangement, three parts of the J-Type immediate then line up with other instructions formats.

The three parts of the J-Type immediate are:

  • Imm[19:12], which lines up with UI-type format Imm[19:12] of its larger Imm[31:12]
  • Imm[10:1], which lines up with the I-Type format Imm[10:1] of its larger Imm[11:0]
  • Imm[20], which lines up with the sign bit for I-, UI-, S-, B- Types

That covers J-Type immediate Imm[20:12] and Imm[10:1], so what's left to encode/explain then is:

  • Imm[0], however, since all branch addresses must be even it is simply take as zero rather than encoded in the instruction
  • Imm[11], goes where it can!

As every other instruction field has a mapping, what's left in the instruction is Inst[20], so that is what Imm[11] is mapped to.  Despite being a somewhat odd position choice, it costs the hardware little overhead to move that bit to the right position while also putting a zero in the low bit position.

See also the two related answers here at this question: Why are RISC-V S-B and U-J instruction types encoded in this way?

Erik Eidt
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  • Thanks. More detailedly, instruction is at least 16 bits (2 bytes), so 'addresses must be even'. – zg c May 31 '23 at 10:46