MIPS procesor datapath for sub instruction

Question

Consider this data path for a single-cycle 32-bit MIPS processor. Suppose the register of the processor have the following values $t2 = 0x12, $t3 = 0x82, $s1 = 0x1. Furthermore suppose that the processor is executing the instruction sub $s1,$t2, $t3 Datapath for mipswhich is located at address 0x40000120. What would the value for the signal D( shown in the figure) be? I have understood that you get the value as address + 4 + ( 2<< imm) However we do not have a imm value here. Is the D signal then just address + 4 ( 0x40000124)?

Also would the signal A be 0x1?

Don't guess. Work backwards from the `D` datapath mark to see what operations are performed on what inputs. Do the same with the `A` datapath mark — work backward to see where the signal is coming from. You should be able to determine the width of each of those datapaths. The diagram you're working with doesn't have directional arrows on the control signals and datapaths, but many online do, for example: https://stackoverflow.com/questions/33334521/extending-mips-datapath-to-implement-sll-and-srl . Once you understand the direction of flow you can work backwards to answers. — Erik Eidt, Jun 08 '23 at 17:11
You can also reason the direction of flow by differentiating consumers and producers for each block in the diagram. Flow goes from producers to consumers, so if you understand what a block does, you'll also know which of its connections are producers vs. consumers. — Erik Eidt, Jun 08 '23 at 17:14
@ErikEidt Thank you. So that means that in this case the control signal for branch will tell the pc to accept PC+4 and therefor the signal for D is 0x40000124? — ee ss, Jun 09 '23 at 08:28
Just because the mux chooses PC+4 instead of D, that doesn't mean that D=PC+4! D is still address + 4 + (2< — Erik Eidt, Jun 09 '23 at 12:48
@ErikEidt so in this case the value for the D signal is unknown because we do not have a imm? I have understood that the mux chooses PC+4 instead of D, however what would the value for D be then? — ee ss, Jun 09 '23 at 12:53
The value can be identified exactly, by following what the hardware does. Sure there is no `imm` field in R-Type instructions, but that hardware looks at the instruction as if it is an I-Type, so there is an `imm`, which is simply the lower 16 bits of the instruction. Yes, the D computation is irrelevant to a sub instruction, so that's why the mux will discard D. However, D still has an exact value that you can compute. You need to know value of the lower 16 bits of the instruction, as that is what D will use for imm<<2. — Erik Eidt, Jun 09 '23 at 12:54
Can you reason what the `imm` value is? You'll need to know how the `sub` instruction is encoded; you can manually assemble that into machine code or use an assembler such as MARS. — Erik Eidt, Jun 09 '23 at 13:02

Erik Eidt · Accepted Answer · 2023-06-09T13:23:46.780

I have understood that you get the value as address + 4 + (imm<<2) However we do not have a imm value here. Is the D signal then just address + 4 ( 0x40000124)?

No, the hardware computes exactly the formula you stated (well using signextend16to32(imm)<<2 not 2<<imm) — as if this instruction did indeed have an immediate. To find the value for D, you need to decode the subtraction instruction as if using the I-Type format, which is to say the lower 16 bits of that subtraction instruction.

Of course, because this is not an I-Type instruction, the control signal for Branch will tell the pc to accept PC+4 not the other formula calculated for the D datapath.

In effect, there's enough hardware there to execute any instruction, put another way, the hardware has the union of all components needed to execute every possible instruction. It is common then, for some calculations to happen that are later ignored, since that hardware and calculation made simply they don't apply to every instruction.

It is easier to tell the hardware to ignore some inappropriate calculation, than to simply not do the calculation. (It is also faster, in that many calculations happen before we know whether or not they're needed. That hardware is there, it runs and costs some power even though its result is only used on taken branch instructions.)

This is the purpose of muxes and control signals that tell the mux what data is relevant to this particular instruction (and hence also what to ignore).

A mux is equivalent to the ?: operator in C or an if-then-else such as

datapath = x ? PC+4 : PC+4+(imm<<2)

or

datapath = if x then PC+4 else PC+4+(imm<<2)

or

if x then
    datapath = PC+4
else
    datapath = PC+4+(imm<<2)

The primary difference being that in C, say, only one side of the ?: or the then/else will execute, whereas in hardware, both sides execute, even though only one is chosen/useful.

For more info on operator execution in various languages, see Eager vs. Short-Circuit

MIPS procesor datapath for sub instruction

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