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I have been looking at this problem, and upon my own attempt, I found 3 data hazards. However, other sources say otherwise.

Find all hazards in the following instructions (MIPS Pipeline):

add $t3, $t1, $t2
sub $t3, $t2, $t1
and $t4, $t3, $t1
or $t0, $t3, $t4
xor $t1, $t4, $t3
sw $t4, 4($t0)

Not only that, but even chatGPT isnt giving any conclusive explanations:

Shivam Singh
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  • ChatGPT is terrible at assembly language. My guess is that the same register names getting reused for different things gives it a hard time. Anyway, hazards depend on your pipeline layout. Perhaps you're assuming a https://en.wikipedia.org/wiki/Classic_RISC_pipeline 5-stage pipeline, like many real MIPS CPUs used? Looks like the last 4 instructions each read a register written by an earlier instruction, and the second has a WAW hazard with the first, among others. You just have to look at recent writes of input and output registers. (And for WAR hazards, earlier reads of the dst.) – Peter Cordes Jul 20 '23 at 01:30
  • I find it hilarious that ChatGPT can't do it right, considering how compilers do it so well. I'm surprised at this point when you ask it "Write me an assembly program that does this" it doesn't just write a C program and then disassemble it – puppydrum64 Jul 20 '23 at 15:13
  • @puppydrum64: How would ChatGPT compile a C program and get disassembly? It's *just* a large language model; it can't decide to run other tools. The only thing it can do is output text, so it has to invent it all itself. A differently designed AI that could decide to use external tools separate from its language model could be much better at making real asm, or at least avoiding totally implausible stuff. – Peter Cordes Jul 20 '23 at 15:55
  • Well I guess I don't understand how it works. I thought that ChatGPT could google things to figure out the answer – puppydrum64 Jul 20 '23 at 15:56

1 Answers1

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This is a contrived and silly code sequence.

add $t3, $t1, $t2
sub $t3, $t2, $t1

In the above, $t3 is written by add but then overwritten by sub and without the adds $t3 being ever used.  In and of itself, this does not create a hazard, the data hazards are also known as RAW Hazards, which stands for Read After Write.  In the above, there is only Write After Write, for which MIPS pipelines do not suffer a hazard.

In the next instruction:

and $t4, $t3, $t1

there is one data RAW hazard, on $t3.

When we factor in the next instruction:

or $t0, $t3, $t4

We have two hazards in one instruction, one on $t3 and one on $t4.  Since there are two hazards in one instruction, we have to become problem-statement reading experts to determine the answer.  As it is still only one instruction, if you're counting instructions that have hazards, it counts as one, but if you're counting hazards themselves, it counts as two.

With:

xor $t1, $t4, $t3

We have a hazard on $t4, but $t3 has made it through the pipeline and back to the register file, if you use the common implementation detail that the register file can read current-cycle-written results.

And finally:

sw $t4, 4($t0)

has a RAW data hazard on $t0.

So, I count 5 RAW hazards, and, 4 instructions that have at least one RAW hazard.

Erik Eidt
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  • Just for my understanding, what makes `and $t4, $t3, $t1` a RAW hazard on `$t3`? Is it because the previous instruction outputs to that register, and the pipeline has already started doing the `and $t4, $t3, $t1` before `sub $t3, $t2, $t1` has finished? – puppydrum64 Jul 20 '23 at 13:16
  • @puppydrum64, Let's say a first instruction is fetched (IF) at cycle 1, then its result doesn't get into the register file until its WB stage, cycle 5. *This creates a RAW hazard for any instruction that reads that same register in cycle 3 **or cycle 4***. – Erik Eidt Jul 20 '23 at 14:47
  • That can only happen for a second instruction (whose ID is in cycle 3) and a third instruction (whose ID is in cycle 4); they will read stale values in their ID stage; while a fourth instruction (whose ID is in cycle 5) will read the proper value (and only then by supporting overlapping ID read with WB write to obtain the architecturally current value). – Erik Eidt Jul 20 '23 at 14:47
  • However, let's note that the first instruction's EX stage happens in cycle 3, so its actual ALU result is in the processor somewhere by cycle 4. A second instruction's EX stage is in cycle 4, so a forward/bypass mechanism can mitigate the 2 cycle/instruction delay of the RAW hazard. – Erik Eidt Jul 20 '23 at 14:48
  • For ALU operations, an EX->EX bypass mitigates RAW hazards. It gets more complicated with loads since they produce result values in MEM stage (4th stage), so generally speaking an extra cycle delay is required for using the loaded value even with a proper bypass (MEM->EX). Stores are again also more complicated as they ultimately consume one value in the EX stage (the base address value) but also another in the MEM stage (the value to store); a store of the same register that is loaded in the immediately prior instruction does not need that extra cycle delay with a MEM->MEM bypass. – Erik Eidt Jul 20 '23 at 14:59
  • I think that makes sense. It's kind of like a race condition except the CPU is in a race with itself. So if I understand correctly, the `and` statement is treating `$t3` like the `sub` never happened since it's reading `$t3` as it was before the results of the `sub` were written back into it. Which will cause `$t4` to have the wrong result when the CPU does `or $t0, $t3, $t4`. – puppydrum64 Jul 20 '23 at 15:04
  • @puppydrum64, yes exactly. – Erik Eidt Jul 20 '23 at 15:05