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I am having trouble performing logical instructions on the ARMv8-a architecture.

for example, "and x13, x13, #0x0000CCCC0000CCCC" or "and x13, x13, #0x0A0A0A0A0A0A0A0A" results in an immediate out of range error, but "and x13, x13, #0x5555555555555555" or "and x13, x13, #0xFFFFFFFFFFFFFFFD" does not. In this way, sometimes a range error occurs during a 64-bit immediate and sometimes not.

I looked up the official documentation, According to https://developer.arm.com/documentation/den0024/a/An-Introduction-to-the-ARMv8-Instruction-Sets/The-ARMv8-instruction-sets, "Logical instructions generally accept a 32-bit or 64-bit constant, which has some constraints in its encoding." What are these "some constraints" and where can I see them? I cannot find that constraints.

DAMPER
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  • `and x13, x13, 0xFFFFFFFFFFFFFFFFFD` isn't encodeable, GAS complains about it, as expected because it's not a repeating bit-pattern. Maybe you meant `and x13, x13, 0xFFFFFFFFFFFFFFF` (without the trailing `D` and with two fewer `F` characters, so it's a 64-bit constant instead of 76-bit.) – Peter Cordes Aug 16 '23 at 07:57
  • sorry, it was "'AND x13, x13, #0xFFFFFFFFFFFFFFFD'". – DAMPER Aug 16 '23 at 08:02
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    0xFFFFFFFFFFFFFFFD doesn't have all its bits contiguous in the one 64-bit chunk (it's `0b111...01`), but as the linked duplicate explains, the encoding also allows a rotate count. – Peter Cordes Aug 16 '23 at 15:31
  • Interestingly, `and x13, x13, #0` and `#-1` aren't encodeable. That's good, they didn't waste coding space on useless immediates: `0` as an operand for bitwise-booleans is either a NOP or a zeroing operation, and `eor x13, x13, x13` or `sub` can still produce a zero with a data-dependency on the input (`std::memory_order_consume`) in one instruction. And that's so rarely needed it would have been fine to need two instructions for that. – Peter Cordes Aug 16 '23 at 15:41

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